minicc.git/asm/intel64, branch master
Minimal Incomplete Compiler Collection
https://reichwein.it/cgit/minicc.git/atom?h=master
2020-11-28T12:41:39Z
Complete: Shift Left and Shift Right
2020-11-28T12:41:39Z
Roland Reichwein
mail@reichwein.it
2020-11-28T12:41:39Z
urn:sha1:d7b8b5c0b8751caf5b51622f2329b363ecabc267
Implemented MOVSX - Move With Sign-Extension
2020-11-28T11:38:49Z
Roland Reichwein
mail@reichwein.it
2020-11-28T11:38:49Z
urn:sha1:a632cce380a853f5400111e19e1380982ed8a7fd
Implemented SETcc - Set Byte On Condition
2020-11-28T11:08:10Z
Roland Reichwein
mail@reichwein.it
2020-11-28T11:08:10Z
urn:sha1:108569319d85a1832700f70ae6c93d7e926dfa92
Implemented CMOVcc - Conditional Move
2020-11-28T10:53:02Z
Roland Reichwein
mail@reichwein.it
2020-11-28T10:53:02Z
urn:sha1:f82ed28acbbbf10a243e44dcbc4ddeebc0dde446
Added CMP
2020-11-27T21:51:50Z
Roland Reichwein
mail@reichwein.it
2020-11-27T21:51:50Z
urn:sha1:541a2dffdcb02063f71d21af22aebbd293c9e49f
Implement shl reg, cl
2020-11-24T22:04:36Z
Roland Reichwein
mail@reichwein.it
2020-11-24T22:04:36Z
urn:sha1:f9885f48fc968c4122f2ed231a7a48938cc7206c
Implement Shift Left (WIP)
2020-11-24T09:00:47Z
Roland Reichwein
mail@reichwein.it
2020-11-24T09:00:47Z
urn:sha1:926b44301aa339b7a204f709959ee44b6ee95902
Add Subtract, generalized binary operations
2020-11-23T21:01:49Z
Roland Reichwein
mail@reichwein.it
2020-11-23T21:01:49Z
urn:sha1:61db05a4127790da3219fccce87c34aa890d1d08
Generalize Add / Mul, Integer promotion, tests
2020-11-22T21:14:23Z
Roland Reichwein
mail@reichwein.it
2020-11-22T21:14:23Z
urn:sha1:ff69e8cab318101843cd8b49a0cb04df9763e10f
Fix frame pointer - pop was too early
2020-11-22T13:09:58Z
Roland Reichwein
mail@reichwein.it
2020-11-22T13:09:58Z
urn:sha1:fd8517e10937a5b72ed839ce900306f281d74b7d