1 files changed, 42 insertions, 0 deletions
diff --git a/asm/intel64/sub.cpp b/asm/intel64/sub.cpp
new file mode 100644
index 0000000..e055ee9
--- /dev/null
+++ b/asm/intel64/sub.cpp
@@ -0,0 +1,42 @@
+#include "sub.h"
+
+#include "codes.h"
+
+#include <asm/assembler.h>
+#include <asm/operators.h>
+
+using namespace std::string_literals;
+
+Op_sub::Op_sub(Asm::Args& args)
+{
+ if (args[0].type() == typeid(Asm::Args::Register32) &&
+     std::any_cast<Asm::Args::Register32>(args[0]).name() == "eax" &&
+     args[1].type() == typeid(Asm::Args::Immediate32))
+ { // sub eax, imm32 (before "sub reg32, imm32"! It's shorter.)
+  machine_code = std::vector<uint8_t>{ 0x2D } + std::any_cast<Asm::Args::Immediate32>(args[1]).getCode();
+ } else if (args[0].type() == typeid(Asm::Args::Register32) &&
+     args[1].type() == typeid(Asm::Args::Immediate32))
+ { // sub reg32, imm32
+  machine_code = std::vector<uint8_t>{ 0x81 } + ModRM("/5", std::any_cast<Asm::Args::Register32>(args[0]).name()) + std::any_cast<Asm::Args::Immediate32>(args[1]).getCode();
+ } else if (args[0].type() == typeid(Asm::Args::Register64) &&
+            std::any_cast<Asm::Args::Register64>(args[0]).name() == "rax"  &&
+            args[1].type() == typeid(Asm::Args::Immediate32))
+ { // sub reg, imm32
+  machine_code = REX("W") + machine_code = std::vector<uint8_t>{ 0x81 } + ModRM("/5", std::any_cast<Asm::Args::Register32>(args[0]).name()) + std::any_cast<Asm::Args::Immediate32>(args[1]).getCode();
+ } else {
+  throw std::runtime_error("Unimplemented: sub "s + args[0].type().name() + " "s + args[1].type().name());
+ }
+}
+
+namespace {
+
+bool registered {
+ registerOp(mangleName<Asm::Args::Register32, Asm::Args::Immediate32>("sub"), [](Asm::Args& args) -> std::shared_ptr<Op>{
+                             return std::make_shared<Op_sub>(args);
+                             }) &&
+ registerOp(mangleName<Asm::Args::Register64, Asm::Args::Immediate32>("sub"), [](Asm::Args& args) -> std::shared_ptr<Op>{
+                             return std::make_shared<Op_sub>(args);
+                             })
+};
+
+}