From e4603f28a2aa4847beb141534d7497ce793629f3 Mon Sep 17 00:00:00 2001
From: Roland Reichwein <mail@reichwein.it>
Date: Sat, 7 Sep 2024 18:54:48 +0200
Subject: Added insns

---
 asm/arm/instruction.h | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

(limited to 'asm/arm/instruction.h')

diff --git a/asm/arm/instruction.h b/asm/arm/instruction.h
index d6c8b12..d64679a 100644
--- a/asm/arm/instruction.h
+++ b/asm/arm/instruction.h
@@ -113,6 +113,9 @@ namespace {
  std::shared_ptr<Operand> imm(uint8_t size, uint8_t pos, uint8_t factor = 1, uint32_t code0_is_value = 0, const std::vector<uint32_t>& invalid_values = {}){ return std::make_shared<Immediate>(size, pos); }
  std::shared_ptr<Operand> label(uint8_t size, uint8_t pos, uint8_t factor = 1, bool is_signed = false){ return std::make_shared<Immediate>(size, pos); }
  std::shared_ptr<Operand> label(uint8_t size, const std::vector<uint8_t>& bits, uint32_t flip_mask, uint8_t factor = 1, bool is_signed = false){ throw std::runtime_error("Unimplemented: label w/ flipmask"); }
+ // reg size 3: arm register 0-7
+ // reg size 4: arm register 0-15
+ // reg size 8: arm special registers for insns msr, mrs
  // reg_list_ref_index, see LDM
  std::shared_ptr<Operand> reg(uint8_t size, uint8_t pos, std::optional<uint8_t> reg_list_ref_index = std::nullopt) { return std::make_shared<Register>(size, pos); }
  std::shared_ptr<Operand> reg(uint32_t mask) { return std::make_shared<Register>(mask); }
@@ -144,7 +147,7 @@ namespace {
  // TODO: consistency checks:
  // * all bits in an instruction defined
  // * unambiguous patterns
- //   - except: alternative syntax, which needs to be same as other pattern
+ //   - except: alternative syntax, which needs to be same as exactly 1 other pattern
  std::vector<Instruction> insns{
   {"adcs", 2, Pattern(0x4140, high_bits(10)), Operands{optional(same_reg(1)), reg(3, 0), reg(3, 3)}}, // T1
   {"adds", 2, Pattern(0x1C00, high_bits(8)), Operands{reg(3, 0), reg(3, 3), imm(3, 6)}}, // T1
@@ -206,10 +209,10 @@ namespace {
   {"movs", 2, Pattern(0x4080, high_bits(10)).alternative_syntax(), Operands{reg(3, 0), same_reg(0), prefixed(reg(3, 3), "lsl ")}}, // T1
   {"movs", 2, Pattern(0x40C0, high_bits(10)).alternative_syntax(), Operands{reg(3, 0), same_reg(0), prefixed(reg(3, 3), "lsr ")}}, // T1
   {"movs", 2, Pattern(0x41C0, high_bits(10)).alternative_syntax(), Operands{reg(3, 0), same_reg(0), prefixed(reg(3, 3), "ror ")}}, // T1
-  //{"mrs", 2,
+  {"mrs", 4, Pattern(0xF3EF8000, high_bits(20)), Operands{reg(4, 8), reg(8, 0)}}, // T1
+  {"msr", 4, Pattern(0xF3808800, 0xFFF0FF00), Operands{reg(4, 16), reg(8, 0)}}, // T1
 
   {"rors", 2, Pattern(0x41C0, high_bits(10)), Operands{reg(3, 0), same_reg(0), reg(3, 3)}}, // T1
  };
 };
 
-
-- 
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