From 031bfef600e7021c8bd72e2e663f368e7386b131 Mon Sep 17 00:00:00 2001
From: Roland Reichwein <mail@reichwein.it>
Date: Wed, 18 Nov 2020 17:55:27 +0100
Subject: Added Asm ops

---
 asm/intel64/and.cpp | 84 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 84 insertions(+)
 create mode 100644 asm/intel64/and.cpp

(limited to 'asm/intel64/and.cpp')

diff --git a/asm/intel64/and.cpp b/asm/intel64/and.cpp
new file mode 100644
index 0000000..a2e110b
--- /dev/null
+++ b/asm/intel64/and.cpp
@@ -0,0 +1,84 @@
+#include "and.h"
+
+#include "codes.h"
+
+#include <asm/assembler.h>
+#include <asm/operators.h>
+
+#include <asm/intel64/codes.h>
+
+using namespace std::string_literals;
+
+Op_and::Op_and(const Asm::Args& args)
+{
+ if (args[0].type() == typeid(Asm::Args::Register8) && args[1].type() == typeid(Asm::Args::Register8)) { // and reg8, reg8
+  // r/m8, r8: ModRM:r/m (w), ModRM:reg (r)
+  machine_code = std::vector<uint8_t>{ 0x20 } +
+   ModRM(std::any_cast<Asm::Args::Register8>(args[1]).name(), std::any_cast<Asm::Args::Register8>(args[0]).name());
+
+ } else if (args[0].type() == typeid(Asm::Args::Register32) && args[1].type() == typeid(Asm::Args::Register32)) { // and reg32, reg32
+  // r/m32, r32: ModRM:r/m (w), ModRM:reg (r)
+  machine_code = std::vector<uint8_t>{ 0x21 } +
+   ModRM(std::any_cast<Asm::Args::Register32>(args[1]).name(), std::any_cast<Asm::Args::Register32>(args[0]).name());
+
+ } else if (args[0].type() == typeid(Asm::Args::Register64) && args[1].type() == typeid(Asm::Args::Register64)) { // and reg64, reg64
+  // r/m64, r64: ModRM:r/m (w), ModRM:reg (r)
+  machine_code = REX("W") + std::vector<uint8_t>{ 0x21 } +
+   ModRM(std::any_cast<Asm::Args::Register64>(args[1]).name(), std::any_cast<Asm::Args::Register64>(args[0]).name());
+
+ } else if (args[0].type() == typeid(Asm::Args::Register32) && args[1].type() == typeid(Asm::Args::Immediate32)) { // and reg32, imm32
+  machine_code = std::vector<uint8_t>{ 0x81 } + ModRM("/4", std::any_cast<Asm::Args::Register32>(args[0]).name()) + std::any_cast<Asm::Args::Immediate32>(args[1]).getCode();
+
+ } else if (args[0].type() == typeid(Asm::Args::Register32) && args[1].type() == typeid(Asm::Args::Mem32Ptr64)) { // and reg32, [reg64]
+  machine_code = std::vector<uint8_t>{ 0x23 } + ModRM(std::any_cast<Asm::Args::Register32>(args[0]).name(), std::any_cast<Asm::Args::Mem32Ptr64>(args[1]).reg());
+
+ } else if (args[0].type() == typeid(Asm::Args::Register64) && args[1].type() == typeid(Asm::Args::Mem64Ptr64)) { // and reg64, [reg64]
+  machine_code = REX("W") + std::vector<uint8_t>{ 0x23 } + ModRM(std::any_cast<Asm::Args::Register64>(args[0]).name(), std::any_cast<Asm::Args::Mem64Ptr64>(args[1]).reg());
+
+ } else if (args[0].type() == typeid(Asm::Args::Mem32Ptr64) && args[1].type() == typeid(Asm::Args::Register32)) { // and [reg64], reg32
+  machine_code = std::vector<uint8_t>{ 0x21 } + ModRM(std::any_cast<Asm::Args::Register32>(args[1]).name(), std::any_cast<Asm::Args::Mem32Ptr64>(args[0]).reg());
+
+ } else if (args[0].type() == typeid(Asm::Args::Mem64Ptr64) && args[1].type() == typeid(Asm::Args::Register64)) { // and [reg64], reg64
+  machine_code = REX("W") + std::vector<uint8_t>{ 0x21 } + ModRM(std::any_cast<Asm::Args::Register64>(args[1]).name(), std::any_cast<Asm::Args::Mem64Ptr64>(args[0]).reg());
+
+ } else if (args[0].type() == typeid(Asm::Args::Register64) && args[1].type() == typeid(Asm::Args::Immediate32)) { // and reg64, imm32 (sign-extended)
+  machine_code = REX("W") + std::vector<uint8_t>{ 0x81 } + ModRM("/4", std::any_cast<Asm::Args::Register64>(args[0]).name()) + std::any_cast<Asm::Args::Immediate32>(args[1]).getCode();
+
+ } else {
+  throw std::runtime_error("Unimplemented: and "s + args[0].type().name() + " "s + args[1].type().name());
+ }
+}
+
+namespace {
+
+bool registered {
+ registerOp(mangleName<Asm::Args::Register8, Asm::Args::Register8>("and"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_and>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Register32, Asm::Args::Register32>("and"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_and>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Register64, Asm::Args::Register64>("and"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_and>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Register32, Asm::Args::Immediate32>("and"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_and>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Register32, Asm::Args::Mem32Ptr64>("and"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_and>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Mem32Ptr64, Asm::Args::Register32>("and"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_and>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Register64, Asm::Args::Mem64Ptr64>("and"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_and>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Mem64Ptr64, Asm::Args::Register64>("and"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_and>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Register64, Asm::Args::Immediate32>("and"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_and>(args);
+            })
+};
+
+}
-- 
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