From 031bfef600e7021c8bd72e2e663f368e7386b131 Mon Sep 17 00:00:00 2001
From: Roland Reichwein <mail@reichwein.it>
Date: Wed, 18 Nov 2020 17:55:27 +0100
Subject: Added Asm ops

---
 asm/intel64/bsr.cpp | 47 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 asm/intel64/bsr.cpp

(limited to 'asm/intel64/bsr.cpp')

diff --git a/asm/intel64/bsr.cpp b/asm/intel64/bsr.cpp
new file mode 100644
index 0000000..099c7d2
--- /dev/null
+++ b/asm/intel64/bsr.cpp
@@ -0,0 +1,47 @@
+#include "bsr.h"
+
+#include "codes.h"
+
+#include <asm/assembler.h>
+#include <asm/operators.h>
+
+using namespace std::string_literals;
+
+Op_bsr::Op_bsr(const Asm::Args& args)
+{
+ if (args[0].type() == typeid(Asm::Args::Register32) && args[1].type() == typeid(Asm::Args::Register32)) { // bsr reg32, reg32
+  machine_code = std::vector<uint8_t>{ 0x0F, 0xBD } + ModRM(std::any_cast<Asm::Args::Register32>(args[0]).name(), std::any_cast<Asm::Args::Register32>(args[1]).name());
+
+ } else if (args[0].type() == typeid(Asm::Args::Register64) && args[1].type() == typeid(Asm::Args::Register64)) { // bsr reg64, reg64
+  machine_code = REX("W") + std::vector<uint8_t>{ 0x0F, 0xBD } + ModRM(std::any_cast<Asm::Args::Register64>(args[0]).name(), std::any_cast<Asm::Args::Register64>(args[1]).name());
+
+ } else if (args[0].type() == typeid(Asm::Args::Register32) && args[1].type() == typeid(Asm::Args::Mem32Ptr64)) { // bsr reg32, [reg64]
+  machine_code = std::vector<uint8_t>{ 0x0F, 0xBD } + ModRM(std::any_cast<Asm::Args::Register32>(args[0]).name(), std::any_cast<Asm::Args::Mem32Ptr64>(args[1]).reg());
+
+ } else if (args[0].type() == typeid(Asm::Args::Register64) && args[1].type() == typeid(Asm::Args::Mem64Ptr64)) { // bsr reg64, [reg64]
+  machine_code = REX("W") + std::vector<uint8_t>{ 0x0F, 0xBD } + ModRM(std::any_cast<Asm::Args::Register64>(args[0]).name(), std::any_cast<Asm::Args::Mem64Ptr64>(args[1]).reg());
+
+ } else {
+  throw std::runtime_error("Unimplemented: bsr "s + args[0].type().name() + " "s + args[1].type().name());
+ }
+}
+
+namespace {
+
+bool registered {
+ registerOp(mangleName<Asm::Args::Register32, Asm::Args::Register32>("bsr"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+                             return std::make_shared<Op_bsr>(args);
+                             }) &&
+ registerOp(mangleName<Asm::Args::Register64, Asm::Args::Register64>("bsr"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+                             return std::make_shared<Op_bsr>(args);
+                             }) &&
+ registerOp(mangleName<Asm::Args::Register32, Asm::Args::Mem32Ptr64>("bsr"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+                             return std::make_shared<Op_bsr>(args);
+                             }) &&
+ registerOp(mangleName<Asm::Args::Register64, Asm::Args::Mem64Ptr64>("bsr"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+                             return std::make_shared<Op_bsr>(args);
+                             })
+};
+
+}
+
-- 
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