From 387af55e498970975d77291374e2f5be12a040bd Mon Sep 17 00:00:00 2001 From: Roland Reichwein Date: Fri, 13 Nov 2020 09:34:45 +0100 Subject: Added intel sub, div, idiv --- asm/intel64/div.cpp | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 asm/intel64/div.cpp (limited to 'asm/intel64/div.cpp') diff --git a/asm/intel64/div.cpp b/asm/intel64/div.cpp new file mode 100644 index 0000000..5ed9988 --- /dev/null +++ b/asm/intel64/div.cpp @@ -0,0 +1,43 @@ +#include "div.h" + +#include "codes.h" + +#include +#include + +#include + +using namespace std::string_literals; + +Op_div::Op_div(Asm::Args& args) +{ + if (args[0].type() == typeid(Asm::Args::Register8)) { // div reg8 (accu is al (remainder=ah) <- ah / reg8) + machine_code = std::vector{ 0xF6 } + + ModRM("/6", std::any_cast(args[0]).name()); + } else if (args[0].type() == typeid(Asm::Args::Register32)) { // div reg32 (accu is eax (remainder=edx) <- edx:eax / reg32) + machine_code = std::vector{ 0xF7 } + + ModRM("/6", std::any_cast(args[0]).name()); + } else if (args[0].type() == typeid(Asm::Args::Register64)) { // div reg64 (accu is rax (remainder=rdx) <- rdx:rax / reg64) + machine_code = REX("W") + std::vector{ 0xF7 } + + ModRM("/6", std::any_cast(args[0]).name()); + } else { + throw std::runtime_error("Unimplemented: div "s + args[0].type().name()); + } +} + +namespace { + +bool registered { + registerOp(mangleName("div"), [](Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(args); + }) && + registerOp(mangleName("div"), [](Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(args); + }) && + registerOp(mangleName("div"), [](Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(args); + }) +}; + +} + -- cgit v1.2.3