From 6ab3715ee2622e293f7c4924511f31347b327e6e Mon Sep 17 00:00:00 2001
From: Roland Reichwein <mail@reichwein.it>
Date: Mon, 9 Nov 2020 10:35:00 +0100
Subject: Implement inc instruction, support 64 bit regs

---
 asm/intel64/inc.cpp | 43 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100644 asm/intel64/inc.cpp

(limited to 'asm/intel64/inc.cpp')

diff --git a/asm/intel64/inc.cpp b/asm/intel64/inc.cpp
new file mode 100644
index 0000000..3df9104
--- /dev/null
+++ b/asm/intel64/inc.cpp
@@ -0,0 +1,43 @@
+#include "inc.h"
+
+#include "codes.h"
+
+#include <asm/assembler.h>
+#include <asm/operators.h>
+
+#include <asm/intel64/codes.h>
+
+using namespace std::string_literals;
+
+Op_inc::Op_inc(Asm::Args& args)
+{
+ if (args[0].type() == typeid(Asm::Args::Register8)) { // inc reg8
+  machine_code = std::vector<uint8_t>{ 0xFE } +
+   ModRM("/0", std::any_cast<Asm::Args::Register8>(args[0]).name());
+ } else if (args[0].type() == typeid(Asm::Args::Register32)) { // inc reg32
+  machine_code = std::vector<uint8_t>{ 0xFF } +
+   ModRM("/0", std::any_cast<Asm::Args::Register32>(args[0]).name());
+ } else if (args[0].type() == typeid(Asm::Args::Register64)) { // inc reg64
+  machine_code = REX("W") + std::vector<uint8_t>{ 0xFF } +
+   ModRM("/0", std::any_cast<Asm::Args::Register64>(args[0]).name());
+ } else {
+  throw std::runtime_error("Unimplemented: inc "s + args[0].type().name());
+ }
+}
+
+namespace {
+
+bool registered {
+ registerOp(mangleName<Asm::Args::Register8>("inc"), [](Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_inc>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Register32>("inc"), [](Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_inc>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Register64>("inc"), [](Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_inc>(args);
+            })
+};
+
+}
+
-- 
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