From 32e19781c554c83643fcab4c4f39a6a552c367f5 Mon Sep 17 00:00:00 2001
From: Roland Reichwein <mail@reichwein.it>
Date: Tue, 10 Nov 2020 20:05:04 +0100
Subject: Implemented dec, mul, imul

---
 asm/intel64/mul.cpp | 43 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100644 asm/intel64/mul.cpp

(limited to 'asm/intel64/mul.cpp')

diff --git a/asm/intel64/mul.cpp b/asm/intel64/mul.cpp
new file mode 100644
index 0000000..e4c3489
--- /dev/null
+++ b/asm/intel64/mul.cpp
@@ -0,0 +1,43 @@
+#include "mul.h"
+
+#include "codes.h"
+
+#include <asm/assembler.h>
+#include <asm/operators.h>
+
+#include <asm/intel64/codes.h>
+
+using namespace std::string_literals;
+
+Op_mul::Op_mul(Asm::Args& args)
+{
+ if (args[0].type() == typeid(Asm::Args::Register8)) { // mul reg8 (accu is ax <- al)
+  machine_code = std::vector<uint8_t>{ 0xF6 } +
+   ModRM("/4", std::any_cast<Asm::Args::Register8>(args[0]).name());
+ } else if (args[0].type() == typeid(Asm::Args::Register32)) { // mul reg32 (accu is edx:eax <- eax)
+  machine_code = std::vector<uint8_t>{ 0xF7 } +
+   ModRM("/4", std::any_cast<Asm::Args::Register32>(args[0]).name());
+ } else if (args[0].type() == typeid(Asm::Args::Register64)) { // mul reg64 (accu is rdx:rax <- rax)
+  machine_code = REX("W") + std::vector<uint8_t>{ 0xF7 } +
+   ModRM("/4", std::any_cast<Asm::Args::Register64>(args[0]).name());
+ } else {
+  throw std::runtime_error("Unimplemented: mul "s + args[0].type().name());
+ }
+}
+
+namespace {
+
+bool registered {
+ registerOp(mangleName<Asm::Args::Register8>("mul"), [](Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_mul>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Register32>("mul"), [](Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_mul>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Register64>("mul"), [](Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_mul>(args);
+            })
+};
+
+}
+
-- 
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