From 39bccce4fdd1d5ebe312321c963e0325e4d696c5 Mon Sep 17 00:00:00 2001 From: Roland Reichwein Date: Sat, 21 Nov 2020 21:38:56 +0100 Subject: Bugfixing of stack (WIP) --- asm/intel64/mul.cpp | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'asm/intel64/mul.cpp') diff --git a/asm/intel64/mul.cpp b/asm/intel64/mul.cpp index 5825e2a..14810dc 100644 --- a/asm/intel64/mul.cpp +++ b/asm/intel64/mul.cpp @@ -21,14 +21,17 @@ Op_mul::Op_mul(const Asm::Args& args) machine_code = REX("W") + std::vector{ 0xF7 } + ModRM("/4", std::any_cast(args[0]).name()); } else if (args[0].type() == typeid(Asm::Args::Mem8Ptr64)) { // mul byte ptr [reg64] (accu is ax <- al) + Asm::Args::Mem8Ptr64 ptr{std::any_cast(args[0])}; machine_code = std::vector{ 0xF6 } + - ModRM("/4", std::any_cast(args[0]).reg()); + ModRM("/4", ptr.reg(), ptr.offs()); } else if (args[0].type() == typeid(Asm::Args::Mem32Ptr64)) { // mul dword ptr [reg64] (accu is edx:eax <- eax) + Asm::Args::Mem32Ptr64 ptr{std::any_cast(args[0])}; machine_code = std::vector{ 0xF7 } + - ModRM("/4", std::any_cast(args[0]).reg()); + ModRM("/4", ptr.reg(), ptr.offs()); } else if (args[0].type() == typeid(Asm::Args::Mem64Ptr64)) { // mul qword ptr [reg64] (accu is rdx:rax <- rax) + Asm::Args::Mem64Ptr64 ptr{std::any_cast(args[0])}; machine_code = REX("W") + std::vector{ 0xF7 } + - ModRM("/4", std::any_cast(args[0]).reg()); + ModRM("/4", ptr.reg(), ptr.offs()); } else { throw std::runtime_error("Unimplemented: mul "s + args[0].type().name()); } -- cgit v1.2.3