From 39bccce4fdd1d5ebe312321c963e0325e4d696c5 Mon Sep 17 00:00:00 2001 From: Roland Reichwein Date: Sat, 21 Nov 2020 21:38:56 +0100 Subject: Bugfixing of stack (WIP) --- asm/intel64/or.cpp | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'asm/intel64/or.cpp') diff --git a/asm/intel64/or.cpp b/asm/intel64/or.cpp index c5be55c..27daf07 100644 --- a/asm/intel64/or.cpp +++ b/asm/intel64/or.cpp @@ -30,16 +30,20 @@ Op_or::Op_or(const Asm::Args& args) machine_code = std::vector{ 0x81 } + ModRM("/1", std::any_cast(args[0]).name()) + std::any_cast(args[1]).getCode(); } else if (args[0].type() == typeid(Asm::Args::Register32) && args[1].type() == typeid(Asm::Args::Mem32Ptr64)) { // or reg32, [reg64] - machine_code = std::vector{ 0x0B } + ModRM(std::any_cast(args[0]).name(), std::any_cast(args[1]).reg()); + Asm::Args::Mem32Ptr64 ptr{std::any_cast(args[1])}; + machine_code = std::vector{ 0x0B } + ModRM(std::any_cast(args[0]).name(), ptr.reg(), ptr.offs()); } else if (args[0].type() == typeid(Asm::Args::Register64) && args[1].type() == typeid(Asm::Args::Mem64Ptr64)) { // or reg64, [reg64] - machine_code = REX("W") + std::vector{ 0x0B } + ModRM(std::any_cast(args[0]).name(), std::any_cast(args[1]).reg()); + Asm::Args::Mem64Ptr64 ptr{std::any_cast(args[1])}; + machine_code = REX("W") + std::vector{ 0x0B } + ModRM(std::any_cast(args[0]).name(), ptr.reg(), ptr.offs()); } else if (args[0].type() == typeid(Asm::Args::Mem32Ptr64) && args[1].type() == typeid(Asm::Args::Register32)) { // or [reg64], reg32 - machine_code = std::vector{ 0x09 } + ModRM(std::any_cast(args[1]).name(), std::any_cast(args[0]).reg()); + Asm::Args::Mem32Ptr64 ptr{std::any_cast(args[0])}; + machine_code = std::vector{ 0x09 } + ModRM(std::any_cast(args[1]).name(), ptr.reg(), ptr.offs()); } else if (args[0].type() == typeid(Asm::Args::Mem64Ptr64) && args[1].type() == typeid(Asm::Args::Register64)) { // or [reg64], reg64 - machine_code = REX("W") + std::vector{ 0x09 } + ModRM(std::any_cast(args[1]).name(), std::any_cast(args[0]).reg()); + Asm::Args::Mem64Ptr64 ptr{std::any_cast(args[0])}; + machine_code = REX("W") + std::vector{ 0x09 } + ModRM(std::any_cast(args[1]).name(), ptr.reg(), ptr.offs()); } else if (args[0].type() == typeid(Asm::Args::Register64) && args[1].type() == typeid(Asm::Args::Immediate32)) { // or reg64, imm32 (sign-extended) machine_code = REX("W") + std::vector{ 0x81 } + ModRM("/1", std::any_cast(args[0]).name()) + std::any_cast(args[1]).getCode(); -- cgit v1.2.3