From 926b44301aa339b7a204f709959ee44b6ee95902 Mon Sep 17 00:00:00 2001 From: Roland Reichwein Date: Tue, 24 Nov 2020 10:00:47 +0100 Subject: Implement Shift Left (WIP) --- asm/intel64/rcr.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'asm/intel64/rcr.cpp') diff --git a/asm/intel64/rcr.cpp b/asm/intel64/rcr.cpp index 27b688c..c2bc532 100644 --- a/asm/intel64/rcr.cpp +++ b/asm/intel64/rcr.cpp @@ -15,17 +15,17 @@ Op_rcr::Op_rcr(const Asm::Args& args) if (args[0].type() == typeid(Asm::Args::Register8)) { // rcr reg8, 1 machine_code = std::vector{ 0xD0 } + ModRM("/3", std::any_cast(args[0]).name()); } else if (args[0].type() == typeid(Asm::Args::Register32)) { // rcr reg32, 1 - machine_code = std::vector{ 0xD1 } + ModRM("/3", std::any_cast(args[0]).name()); + machine_code = std::vector{ 0xD1 } + ModRM("/3", std::any_cast(args[0]).name()); } else if (args[0].type() == typeid(Asm::Args::Register64)) { // rcr reg64, 1 - machine_code = REX("W") + std::vector{ 0xD1 } + ModRM("/3", std::any_cast(args[0]).name()); + machine_code = REX("W") + std::vector{ 0xD1 } + ModRM("/3", std::any_cast(args[0]).name()); } } else { // general version >= 2 bits shift if (args[0].type() == typeid(Asm::Args::Register8)) { // rcr reg8, imm8 machine_code = std::vector{ 0xC0 } + ModRM("/3", std::any_cast(args[0]).name()) + shift_offset; } else if (args[0].type() == typeid(Asm::Args::Register32)) { // rcr reg32, imm8 - machine_code = std::vector{ 0xC1 } + ModRM("/3", std::any_cast(args[0]).name()) + shift_offset; + machine_code = std::vector{ 0xC1 } + ModRM("/3", std::any_cast(args[0]).name()) + shift_offset; } else if (args[0].type() == typeid(Asm::Args::Register64)) { // rcr reg64, imm8 - machine_code = REX("W") + std::vector{ 0xC1 } + ModRM("/3", std::any_cast(args[0]).name()) + shift_offset; + machine_code = REX("W") + std::vector{ 0xC1 } + ModRM("/3", std::any_cast(args[0]).name()) + shift_offset; } } -- cgit v1.2.3