From 031bfef600e7021c8bd72e2e663f368e7386b131 Mon Sep 17 00:00:00 2001
From: Roland Reichwein <mail@reichwein.it>
Date: Wed, 18 Nov 2020 17:55:27 +0100
Subject: Added Asm ops

---
 asm/intel64/ror.cpp | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 61 insertions(+)
 create mode 100644 asm/intel64/ror.cpp

(limited to 'asm/intel64/ror.cpp')

diff --git a/asm/intel64/ror.cpp b/asm/intel64/ror.cpp
new file mode 100644
index 0000000..70a7a6b
--- /dev/null
+++ b/asm/intel64/ror.cpp
@@ -0,0 +1,61 @@
+#include "ror.h"
+
+#include "codes.h"
+
+#include <asm/assembler.h>
+#include <asm/operators.h>
+
+using namespace std::string_literals;
+
+Op_ror::Op_ror(const Asm::Args& args)
+{
+ if (args[1].type() == typeid(Asm::Args::Immediate8)) {
+  std::vector<uint8_t> shift_offset{std::any_cast<Asm::Args::Immediate8>(args[1]).getCode()};
+  if (shift_offset == std::vector<uint8_t>{ 0x01 }) { // 1 bit version is shorter
+   if (args[0].type() == typeid(Asm::Args::Register8)) { // ror reg8, 1
+    machine_code = std::vector<uint8_t>{ 0xD0 } + ModRM("/1", std::any_cast<Asm::Args::Register8>(args[0]).name());
+   } else if (args[0].type() == typeid(Asm::Args::Register32)) { // ror reg32, 1
+    machine_code = std::vector<uint8_t>{ 0xD1 } + ModRM("/1", std::any_cast<Asm::Args::Register8>(args[0]).name());
+   } else if (args[0].type() == typeid(Asm::Args::Register64)) { // ror reg64, 1
+    machine_code = REX("W") + std::vector<uint8_t>{ 0xD1 } + ModRM("/1", std::any_cast<Asm::Args::Register8>(args[0]).name());
+   }
+  } else { // general version >= 2 bits shift
+   if (args[0].type() == typeid(Asm::Args::Register8)) { // ror reg8, imm8
+    machine_code = std::vector<uint8_t>{ 0xC0 } + ModRM("/1", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset;
+   } else if (args[0].type() == typeid(Asm::Args::Register32)) { // ror reg32, imm8
+    machine_code = std::vector<uint8_t>{ 0xC1 } + ModRM("/1", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset;
+   } else if (args[0].type() == typeid(Asm::Args::Register64)) { // ror reg64, imm8
+    machine_code = REX("W") + std::vector<uint8_t>{ 0xC1 } + ModRM("/1", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset;
+   }
+  }
+
+ } else {
+  throw std::runtime_error("Unimplemented: ror "s + args[0].type().name() + " "s + args[1].type().name());
+ }
+}
+
+namespace {
+
+bool registered {
+ registerOp(mangleName<Asm::Args::Register8, Asm::Args::Immediate8>("ror"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+                             return std::make_shared<Op_ror>(args);
+                             }) &&
+ registerOp(mangleName<Asm::Args::Register32, Asm::Args::Immediate8>("ror"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+                             return std::make_shared<Op_ror>(args);
+                             }) &&
+ registerOp(mangleName<Asm::Args::Register64, Asm::Args::Immediate8>("ror"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+                             return std::make_shared<Op_ror>(args);
+                             }) &&
+ registerOp(mangleName<Asm::Args::Mem8Ptr64, Asm::Args::Immediate8>("ror"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+                             return std::make_shared<Op_ror>(args);
+                             }) &&
+ registerOp(mangleName<Asm::Args::Mem32Ptr64, Asm::Args::Immediate8>("ror"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+                             return std::make_shared<Op_ror>(args);
+                             }) &&
+ registerOp(mangleName<Asm::Args::Mem64Ptr64, Asm::Args::Immediate8>("ror"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+                             return std::make_shared<Op_ror>(args);
+                             })
+};
+
+}
+
-- 
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