From 61db05a4127790da3219fccce87c34aa890d1d08 Mon Sep 17 00:00:00 2001
From: Roland Reichwein <mail@reichwein.it>
Date: Mon, 23 Nov 2020 22:01:49 +0100
Subject: Add Subtract, generalized binary operations

---
 asm/intel64/sub.cpp | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

(limited to 'asm/intel64/sub.cpp')

diff --git a/asm/intel64/sub.cpp b/asm/intel64/sub.cpp
index 2447c15..9efc644 100644
--- a/asm/intel64/sub.cpp
+++ b/asm/intel64/sub.cpp
@@ -14,15 +14,22 @@ Op_sub::Op_sub(const Asm::Args& args)
      args[1].type() == typeid(Asm::Args::Immediate32))
  { // sub eax, imm32 (before "sub reg32, imm32"! It's shorter.)
   machine_code = std::vector<uint8_t>{ 0x2D } + std::any_cast<Asm::Args::Immediate32>(args[1]).getCode();
- } else if (args[0].type() == typeid(Asm::Args::Register32) &&
-     args[1].type() == typeid(Asm::Args::Immediate32))
- { // sub reg32, imm32
+
+ } else if (args[0].type() == typeid(Asm::Args::Register32) && args[1].type() == typeid(Asm::Args::Immediate32)) { // sub reg32, imm32
   machine_code = std::vector<uint8_t>{ 0x81 } + ModRM("/5", std::any_cast<Asm::Args::Register32>(args[0]).name()) + std::any_cast<Asm::Args::Immediate32>(args[1]).getCode();
+
+ } else if (args[0].type() == typeid(Asm::Args::Register32) && args[1].type() == typeid(Asm::Args::Mem32Ptr64)) { // sub reg32, [reg64]
+  machine_code = std::vector<uint8_t>{ 0x2B } + ModRM(std::any_cast<Asm::Args::Register32>(args[0]).name(), std::any_cast<Asm::Args::Mem32Ptr64>(args[1]).reg());
+
+ } else if (args[0].type() == typeid(Asm::Args::Register16) && args[1].type() == typeid(Asm::Args::Mem16Ptr64)) { // sub reg16, [reg64]
+  machine_code = OpSizePrefix() + std::vector<uint8_t>{ 0x2B } + ModRM(std::any_cast<Asm::Args::Register16>(args[0]).name(), std::any_cast<Asm::Args::Mem16Ptr64>(args[1]).reg());
+
  } else if (args[0].type() == typeid(Asm::Args::Register64) &&
             std::any_cast<Asm::Args::Register64>(args[0]).name() == "rax"  &&
             args[1].type() == typeid(Asm::Args::Immediate32))
  { // sub reg, imm32
   machine_code = REX("W") + machine_code = std::vector<uint8_t>{ 0x81 } + ModRM("/5", std::any_cast<Asm::Args::Register32>(args[0]).name()) + std::any_cast<Asm::Args::Immediate32>(args[1]).getCode();
+
  } else {
   throw std::runtime_error("Unimplemented: sub "s + args[0].type().name() + " "s + args[1].type().name());
  }
@@ -35,6 +42,12 @@ bool registered {
                              return std::make_shared<Op_sub>(args);
                              }) &&
  registerOp(mangleName<Asm::Args::Register64, Asm::Args::Immediate32>("sub"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+                             return std::make_shared<Op_sub>(args);
+                             }) &&
+ registerOp(mangleName<Asm::Args::Register16, Asm::Args::Mem16Ptr64>("sub"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+                             return std::make_shared<Op_sub>(args);
+                             }) &&
+ registerOp(mangleName<Asm::Args::Register32, Asm::Args::Mem32Ptr64>("sub"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
                              return std::make_shared<Op_sub>(args);
                              })
 };
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