From a3b4cd4fdd4340c952eaa00bca9bebf817b901ae Mon Sep 17 00:00:00 2001 From: Roland Reichwein Date: Sun, 15 Nov 2020 18:39:01 +0100 Subject: Fixed unit tests, prepared hierarchical evaluation via stack (WIP) --- asm/intel64/xor.cpp | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) (limited to 'asm/intel64/xor.cpp') diff --git a/asm/intel64/xor.cpp b/asm/intel64/xor.cpp index aba6fb5..1628558 100644 --- a/asm/intel64/xor.cpp +++ b/asm/intel64/xor.cpp @@ -12,9 +12,14 @@ using namespace std::string_literals; Op_xor::Op_xor(const Asm::Args& args) { if (args[0].type() == typeid(Asm::Args::Register8) && args[1].type() == typeid(Asm::Args::Register8)) { // xor reg8, reg8 - // r8, r/m8: ModRM:reg (w), ModRM:r/m (r) - machine_code = std::vector{ 0x32 } + + machine_code = std::vector{ 0x30 } + ModRM(std::any_cast(args[0]).name(), std::any_cast(args[1]).name()); + } else if (args[0].type() == typeid(Asm::Args::Register32) && args[1].type() == typeid(Asm::Args::Register32)) { // xor reg32, reg32 + machine_code = std::vector{ 0x31 } + + ModRM(std::any_cast(args[0]).name(), std::any_cast(args[1]).name()); + } else if (args[0].type() == typeid(Asm::Args::Register64) && args[1].type() == typeid(Asm::Args::Register64)) { // xor reg64, reg64 + machine_code = REX("W") + std::vector{ 0x31 } + + ModRM(std::any_cast(args[0]).name(), std::any_cast(args[1]).name()); } else { throw std::runtime_error("Unimplemented: xor "s + args[0].type().name() + " "s + args[1].type().name()); } @@ -25,6 +30,12 @@ namespace { bool registered { registerOp(mangleName("xor"), [](const Asm::Args& args) -> std::shared_ptr{ return std::make_shared(args); + }) && + registerOp(mangleName("xor"), [](const Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(args); + }) && + registerOp(mangleName("xor"), [](const Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(args); }) }; -- cgit v1.2.3