From 6ab3715ee2622e293f7c4924511f31347b327e6e Mon Sep 17 00:00:00 2001
From: Roland Reichwein <mail@reichwein.it>
Date: Mon, 9 Nov 2020 10:35:00 +0100
Subject: Implement inc instruction, support 64 bit regs

---
 asm/intel64/all_ops.h |  5 +++++
 asm/intel64/codes.cpp |  5 +++++
 asm/intel64/inc.cpp   | 43 +++++++++++++++++++++++++++++++++++++++++++
 asm/intel64/inc.h     | 31 +++++++++++++++++++++++++++++++
 asm/intel64/mov.cpp   |  5 +++++
 5 files changed, 89 insertions(+)
 create mode 100644 asm/intel64/inc.cpp
 create mode 100644 asm/intel64/inc.h

(limited to 'asm/intel64')

diff --git a/asm/intel64/all_ops.h b/asm/intel64/all_ops.h
index 83b654b..59ce624 100644
--- a/asm/intel64/all_ops.h
+++ b/asm/intel64/all_ops.h
@@ -1,5 +1,10 @@
 #pragma once
 
+#include "add.h"
+#include "inc.h"
 #include "int.h"
+#include "jmp.h"
+#include "mov.h"
 #include "nop.h"
 #include "ret.h"
+#include "xor.h"
diff --git a/asm/intel64/codes.cpp b/asm/intel64/codes.cpp
index 5d93a57..21a891c 100644
--- a/asm/intel64/codes.cpp
+++ b/asm/intel64/codes.cpp
@@ -37,6 +37,11 @@ namespace {
   {"ebx", 3}, {"ebp", 5},
   {"ecx", 1}, {"esi", 6},
   {"edx", 2}, {"edi", 7},
+  
+  {"rax", 0}, {"rsp", 4},
+  {"rbx", 3}, {"rbp", 5},
+  {"rcx", 1}, {"rsi", 6},
+  {"rdx", 2}, {"rdi", 7},
  };
 
 }
diff --git a/asm/intel64/inc.cpp b/asm/intel64/inc.cpp
new file mode 100644
index 0000000..3df9104
--- /dev/null
+++ b/asm/intel64/inc.cpp
@@ -0,0 +1,43 @@
+#include "inc.h"
+
+#include "codes.h"
+
+#include <asm/assembler.h>
+#include <asm/operators.h>
+
+#include <asm/intel64/codes.h>
+
+using namespace std::string_literals;
+
+Op_inc::Op_inc(Asm::Args& args)
+{
+ if (args[0].type() == typeid(Asm::Args::Register8)) { // inc reg8
+  machine_code = std::vector<uint8_t>{ 0xFE } +
+   ModRM("/0", std::any_cast<Asm::Args::Register8>(args[0]).name());
+ } else if (args[0].type() == typeid(Asm::Args::Register32)) { // inc reg32
+  machine_code = std::vector<uint8_t>{ 0xFF } +
+   ModRM("/0", std::any_cast<Asm::Args::Register32>(args[0]).name());
+ } else if (args[0].type() == typeid(Asm::Args::Register64)) { // inc reg64
+  machine_code = REX("W") + std::vector<uint8_t>{ 0xFF } +
+   ModRM("/0", std::any_cast<Asm::Args::Register64>(args[0]).name());
+ } else {
+  throw std::runtime_error("Unimplemented: inc "s + args[0].type().name());
+ }
+}
+
+namespace {
+
+bool registered {
+ registerOp(mangleName<Asm::Args::Register8>("inc"), [](Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_inc>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Register32>("inc"), [](Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_inc>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Register64>("inc"), [](Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_inc>(args);
+            })
+};
+
+}
+
diff --git a/asm/intel64/inc.h b/asm/intel64/inc.h
new file mode 100644
index 0000000..0887392
--- /dev/null
+++ b/asm/intel64/inc.h
@@ -0,0 +1,31 @@
+// Increment Register
+
+#pragma once
+
+#include <asm/assembler.h>
+
+class Op_inc: public Op
+{
+public:
+ Op_inc(Asm::Args& args);
+
+public:
+ std::vector<uint8_t> getCode() override
+ {
+  return machine_code;
+ }
+
+ size_t size() override
+ {
+  return machine_code.size();
+ }
+
+ bool optimize() override ///< returns true if changed
+ {
+  return false;
+ }
+
+protected:
+ std::vector<uint8_t> machine_code;
+};
+
diff --git a/asm/intel64/mov.cpp b/asm/intel64/mov.cpp
index 8603fc9..5741170 100644
--- a/asm/intel64/mov.cpp
+++ b/asm/intel64/mov.cpp
@@ -17,6 +17,8 @@ Op_mov::Op_mov(Asm::Args& args)
    ModRM(std::any_cast<Asm::Args::Register8>(args[1]).name(), std::any_cast<Asm::Args::Register8>(args[0]).name());
  } else if (args[0].type() == typeid(Asm::Args::Register32) && args[1].type() == typeid(Asm::Args::Immediate32)) { // mov reg32, imm32
   machine_code = std::vector<uint8_t>{ static_cast<uint8_t>(0xB8 + RegNo(std::any_cast<Asm::Args::Register32>(args[0]).name())) } + std::any_cast<Asm::Args::Immediate32>(args[1]).getCode();
+ } else if (args[0].type() == typeid(Asm::Args::Register64) && args[1].type() == typeid(Asm::Args::Immediate64)) { // mov reg64, imm64
+  machine_code = std::vector<uint8_t>{ REX("W") + static_cast<uint8_t>(0xB8 + RegNo(std::any_cast<Asm::Args::Register64>(args[0]).name())) } + std::any_cast<Asm::Args::Immediate64>(args[1]).getCode();
  } else {
   throw std::runtime_error("Unimplemented: mov "s + args[0].type().name() + " "s + args[1].type().name());
  }
@@ -30,6 +32,9 @@ bool registered {
             }) &&
  registerOp(mangleName<Asm::Args::Register32, Asm::Args::Immediate32>("mov"), [](Asm::Args& args) -> std::shared_ptr<Op>{
                return std::make_shared<Op_mov>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Register64, Asm::Args::Immediate64>("mov"), [](Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_mov>(args);
             })
 };
 
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