From 8f28495ab9a8ebf53868405541e907394895e51f Mon Sep 17 00:00:00 2001
From: Roland Reichwein <mail@reichwein.it>
Date: Sat, 17 Oct 2020 21:45:37 +0200
Subject: Add add

---
 asm/intel64/add.cpp   | 31 +++++++++++++++++++++++++++++++
 asm/intel64/add.h     | 31 +++++++++++++++++++++++++++++++
 asm/intel64/codes.cpp | 17 +++++++++++++++++
 asm/intel64/codes.h   |  8 ++++++++
 4 files changed, 87 insertions(+)
 create mode 100644 asm/intel64/add.cpp
 create mode 100644 asm/intel64/add.h
 create mode 100644 asm/intel64/codes.cpp
 create mode 100644 asm/intel64/codes.h

(limited to 'asm/intel64')

diff --git a/asm/intel64/add.cpp b/asm/intel64/add.cpp
new file mode 100644
index 0000000..dc5c704
--- /dev/null
+++ b/asm/intel64/add.cpp
@@ -0,0 +1,31 @@
+#include "add.h"
+
+#include "codes.h"
+
+#include <asm/assembler.h>
+#include <asm/operators.h>
+
+using namespace std::string_literals;
+
+Op_add::Op_add(AsmArgs& args)
+{
+ if (args[0].type() == typeid(Register32) && std::any_cast<Register32>(args[0]).name() == "eax" && args[1].type() == typeid(Immediate32)) { // add eax, imm32
+  machine_code = std::vector<uint8_t>{ 0x05 } + std::any_cast<Immediate32>(args[1]).getCode();
+ } else if (args[0].type() == typeid(Register64) && std::any_cast<Register64>(args[0]).name() == "rax"  && args[1].type() == typeid(Immediate32)) { // add rax, imm32
+  machine_code = REX("W") + std::vector<uint8_t>{ 0x05 } + std::any_cast<Immediate32>(args[1]).getCode();
+ } else {
+  throw std::runtime_error("Unimplemented: add "s + args[0].type().name() + " "s + args[1].type().name());
+ }
+}
+
+namespace {
+
+bool registered0 { registerOp(mangleName<Register32, Immediate32>("add"), [](AsmArgs& args) -> std::shared_ptr<Op>{
+                             return std::make_shared<Op_add>(args);
+                             }) };
+// TODO
+bool registered1 { registerOp(mangleName<Register64, Immediate32>("add"), [](AsmArgs& args) -> std::shared_ptr<Op>{
+                             return std::make_shared<Op_add>(args);
+                             }) };
+
+}
diff --git a/asm/intel64/add.h b/asm/intel64/add.h
new file mode 100644
index 0000000..4c6b589
--- /dev/null
+++ b/asm/intel64/add.h
@@ -0,0 +1,31 @@
+// Integer Addition
+
+#pragma once
+
+#include <asm/assembler.h>
+
+class Op_add: public Op
+{
+public:
+ Op_add(AsmArgs& args);
+
+public:
+ std::vector<uint8_t> getCode() override
+ {
+  return machine_code;
+ }
+
+ size_t size() override
+ {
+  return machine_code.size();
+ }
+
+ bool optimize() override ///< returns true if changed
+ {
+  return false;
+ }
+
+protected:
+ std::vector<uint8_t> machine_code;
+};
+
diff --git a/asm/intel64/codes.cpp b/asm/intel64/codes.cpp
new file mode 100644
index 0000000..a1d9e87
--- /dev/null
+++ b/asm/intel64/codes.cpp
@@ -0,0 +1,17 @@
+#include "codes.h"
+
+// REX prefix: 0b0100WRXB
+std::vector<uint8_t> REX(std::string s) {
+ uint8_t result{0b01000000};
+ if (s == "W")
+  result |= 0b00001000;
+ if (s == "R")
+  result |= 0b00000100;
+ if (s == "X")
+  result |= 0b00000010;
+ if (s == "B")
+  result |= 0b00000001;
+
+ return { result }; 
+}
+
diff --git a/asm/intel64/codes.h b/asm/intel64/codes.h
new file mode 100644
index 0000000..32eff1c
--- /dev/null
+++ b/asm/intel64/codes.h
@@ -0,0 +1,8 @@
+#pragma once
+
+#include <cstdint>
+#include <string>
+#include <vector>
+
+// REX prefix: 0b0100WRXB
+std::vector<uint8_t> REX(std::string s);
-- 
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