From f82ed28acbbbf10a243e44dcbc4ddeebc0dde446 Mon Sep 17 00:00:00 2001 From: Roland Reichwein Date: Sat, 28 Nov 2020 11:53:02 +0100 Subject: Implemented CMOVcc - Conditional Move --- asm/intel64/all_ops.h | 1 + asm/intel64/cmovcc.cpp | 108 +++++++++++++++++++++++++++++++++++++++++++++++++ asm/intel64/cmovcc.h | 31 ++++++++++++++ 3 files changed, 140 insertions(+) create mode 100644 asm/intel64/cmovcc.cpp create mode 100644 asm/intel64/cmovcc.h (limited to 'asm/intel64') diff --git a/asm/intel64/all_ops.h b/asm/intel64/all_ops.h index f9dc05b..a64ae81 100644 --- a/asm/intel64/all_ops.h +++ b/asm/intel64/all_ops.h @@ -5,6 +5,7 @@ #include "bsf.h" #include "bsr.h" #include "cmp.h" +#include "cmovcc.h" #include "dec.h" #include "div.h" #include "idiv.h" diff --git a/asm/intel64/cmovcc.cpp b/asm/intel64/cmovcc.cpp new file mode 100644 index 0000000..d4b84e9 --- /dev/null +++ b/asm/intel64/cmovcc.cpp @@ -0,0 +1,108 @@ +#include "cmovcc.h" + +#include "codes.h" + +#include +#include + +#include + +using namespace std::string_literals; + +namespace { + struct Operation { + std::string name; + OP_T opcode; + }; + + std::vector cmovccOps { + {"cmova", OP_T{ 0x0F, 0x47 }}, + {"cmovae", OP_T{ 0x0F, 0x43 }}, + {"cmovb", OP_T{ 0x0F, 0x42 }}, + {"cmovbe", OP_T{ 0x0F, 0x46 }}, + {"cmovc", OP_T{ 0x0F, 0x42 }}, + {"cmove", OP_T{ 0x0F, 0x44 }}, + {"cmovg", OP_T{ 0x0F, 0x4F }}, + {"cmovge", OP_T{ 0x0F, 0x4D }}, + {"cmovl", OP_T{ 0x0F, 0x4C }}, + {"cmovle", OP_T{ 0x0F, 0x4E }}, + {"cmovna", OP_T{ 0x0F, 0x46 }}, + {"cmovnae",OP_T{ 0x0F, 0x42 }}, + {"cmovnb", OP_T{ 0x0F, 0x43 }}, + {"cmovnbe",OP_T{ 0x0F, 0x47 }}, + {"cmovnc", OP_T{ 0x0F, 0x43 }}, + {"cmovne", OP_T{ 0x0F, 0x45 }}, + {"cmovng", OP_T{ 0x0F, 0x4E }}, + {"cmovnge",OP_T{ 0x0F, 0x4C }}, + {"cmovnl", OP_T{ 0x0F, 0x4D }}, + {"cmovnle",OP_T{ 0x0F, 0x4F }}, + {"cmovno", OP_T{ 0x0F, 0x41 }}, + {"cmovnp", OP_T{ 0x0F, 0x4B }}, + {"cmovns", OP_T{ 0x0F, 0x49 }}, + {"cmovnz", OP_T{ 0x0F, 0x45 }}, + {"cmovo", OP_T{ 0x0F, 0x40 }}, + {"cmovp", OP_T{ 0x0F, 0x4A }}, + {"cmovpe", OP_T{ 0x0F, 0x4A }}, + {"cmovpo", OP_T{ 0x0F, 0x4B }}, + {"cmovs", OP_T{ 0x0F, 0x48 }}, + {"cmovz", OP_T{ 0x0F, 0x44 }}, + }; + + bool registerOps() { + bool result{true}; + for (const auto& cmovccOp: cmovccOps) { + result &= registerOp(mangleName(cmovccOp.name), [&](const Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(cmovccOp.name, args, cmovccOp.opcode); + }); + result &= registerOp(mangleName(cmovccOp.name), [&](const Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(cmovccOp.name, args, cmovccOp.opcode); + }); + result &= registerOp(mangleName(cmovccOp.name), [&](const Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(cmovccOp.name, args, cmovccOp.opcode); + }); + result &= registerOp(mangleName(cmovccOp.name), [&](const Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(cmovccOp.name, args, cmovccOp.opcode); + }); + result &= registerOp(mangleName(cmovccOp.name), [&](const Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(cmovccOp.name, args, cmovccOp.opcode); + }); + result &= registerOp(mangleName(cmovccOp.name), [&](const Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(cmovccOp.name, args, cmovccOp.opcode); + }); + } + return result; + } + + bool registered { + registerOps() + }; +} + +Op_cmovcc::Op_cmovcc(const std::string& name, const Asm::Args& args, const OP_T& opcode) +{ + if (args[0].type() == typeid(Asm::Args::Register16) && args[1].type() == typeid(Asm::Args::Register16)) { // cmovcc reg16, reg16 + machine_code = OpSizePrefix() + opcode + ModRM(std::any_cast(args[1]).name(), std::any_cast(args[0]).name()); + + } else if (args[0].type() == typeid(Asm::Args::Register32) && args[1].type() == typeid(Asm::Args::Register32)) { // cmovcc reg32, reg32 + machine_code = opcode + ModRM(std::any_cast(args[1]).name(), std::any_cast(args[0]).name()); + + } else if (args[0].type() == typeid(Asm::Args::Register64) && args[1].type() == typeid(Asm::Args::Register64)) { // cmovcc reg64, reg64 + machine_code = REX("W") + opcode + ModRM(std::any_cast(args[1]).name(), std::any_cast(args[0]).name()); + + } else if (args[0].type() == typeid(Asm::Args::Register16) && args[1].type() == typeid(Asm::Args::Mem16Ptr64)) { // cmovcc reg16, [reg64] + Asm::Args::Mem16Ptr64 ptr{std::any_cast(args[1])}; + machine_code = OpSizePrefix() + opcode + ModRM(std::any_cast(args[0]).name(), ptr.reg(), ptr.offs()); + + } else if (args[0].type() == typeid(Asm::Args::Register32) && args[1].type() == typeid(Asm::Args::Mem32Ptr64)) { // cmovcc reg32, [reg64] + Asm::Args::Mem32Ptr64 ptr{std::any_cast(args[1])}; + machine_code = opcode + ModRM(std::any_cast(args[0]).name(), ptr.reg(), ptr.offs()); + + } else if (args[0].type() == typeid(Asm::Args::Register64) && args[1].type() == typeid(Asm::Args::Mem64Ptr64)) { // cmovcc reg64, [reg64] + Asm::Args::Mem64Ptr64 ptr{std::any_cast(args[1])}; + machine_code = REX("W") + opcode + ModRM(std::any_cast(args[0]).name(), ptr.reg(), ptr.offs()); + + } else { + throw std::runtime_error("Unimplemented: cmovcc "s + args[0].type().name() + " "s + args[1].type().name()); + } +} + diff --git a/asm/intel64/cmovcc.h b/asm/intel64/cmovcc.h new file mode 100644 index 0000000..b11c1b5 --- /dev/null +++ b/asm/intel64/cmovcc.h @@ -0,0 +1,31 @@ +// CMOVcc - Conditional Move + +#pragma once + +#include + +class Op_cmovcc: public Op +{ +public: + Op_cmovcc(const std::string& name, const Asm::Args& args, const OP_T& opcode); + +public: + std::vector getCode() override + { + return machine_code; + } + + size_t size() override + { + return machine_code.size(); + } + + bool optimize() override ///< returns true if changed + { + return false; + } + +protected: + std::vector machine_code; +}; + -- cgit v1.2.3