From 1937e301b6cd185c8ce907b9184142e82e76fda4 Mon Sep 17 00:00:00 2001
From: Roland Reichwein <mail@reichwein.it>
Date: Wed, 18 Nov 2020 18:10:42 +0100
Subject: Implemented asm or

---
 asm/intel64/all_ops.h |  1 +
 asm/intel64/or.cpp    | 84 +++++++++++++++++++++++++++++++++++++++++++++++++++
 asm/intel64/or.h      | 31 +++++++++++++++++++
 3 files changed, 116 insertions(+)
 create mode 100644 asm/intel64/or.cpp
 create mode 100644 asm/intel64/or.h

(limited to 'asm')

diff --git a/asm/intel64/all_ops.h b/asm/intel64/all_ops.h
index 4da0a0b..89313b2 100644
--- a/asm/intel64/all_ops.h
+++ b/asm/intel64/all_ops.h
@@ -15,6 +15,7 @@
 #include "not.h"
 #include "mov.h"
 #include "mul.h"
+#include "or.h"
 #include "pop.h"
 #include "push.h"
 #include "rcl.h"
diff --git a/asm/intel64/or.cpp b/asm/intel64/or.cpp
new file mode 100644
index 0000000..c5be55c
--- /dev/null
+++ b/asm/intel64/or.cpp
@@ -0,0 +1,84 @@
+#include "or.h"
+
+#include "codes.h"
+
+#include <asm/assembler.h>
+#include <asm/operators.h>
+
+#include <asm/intel64/codes.h>
+
+using namespace std::string_literals;
+
+Op_or::Op_or(const Asm::Args& args)
+{
+ if (args[0].type() == typeid(Asm::Args::Register8) && args[1].type() == typeid(Asm::Args::Register8)) { // or reg8, reg8
+  // r/m8, r8: ModRM:r/m (w), ModRM:reg (r)
+  machine_code = std::vector<uint8_t>{ 0x08 } +
+   ModRM(std::any_cast<Asm::Args::Register8>(args[1]).name(), std::any_cast<Asm::Args::Register8>(args[0]).name());
+
+ } else if (args[0].type() == typeid(Asm::Args::Register32) && args[1].type() == typeid(Asm::Args::Register32)) { // or reg32, reg32
+  // r/m32, r32: ModRM:r/m (w), ModRM:reg (r)
+  machine_code = std::vector<uint8_t>{ 0x09 } +
+   ModRM(std::any_cast<Asm::Args::Register32>(args[1]).name(), std::any_cast<Asm::Args::Register32>(args[0]).name());
+
+ } else if (args[0].type() == typeid(Asm::Args::Register64) && args[1].type() == typeid(Asm::Args::Register64)) { // or reg64, reg64
+  // r/m64, r64: ModRM:r/m (w), ModRM:reg (r)
+  machine_code = REX("W") + std::vector<uint8_t>{ 0x09 } +
+   ModRM(std::any_cast<Asm::Args::Register64>(args[1]).name(), std::any_cast<Asm::Args::Register64>(args[0]).name());
+
+ } else if (args[0].type() == typeid(Asm::Args::Register32) && args[1].type() == typeid(Asm::Args::Immediate32)) { // or reg32, imm32
+  machine_code = std::vector<uint8_t>{ 0x81 } + ModRM("/1", std::any_cast<Asm::Args::Register32>(args[0]).name()) + std::any_cast<Asm::Args::Immediate32>(args[1]).getCode();
+
+ } else if (args[0].type() == typeid(Asm::Args::Register32) && args[1].type() == typeid(Asm::Args::Mem32Ptr64)) { // or reg32, [reg64]
+  machine_code = std::vector<uint8_t>{ 0x0B } + ModRM(std::any_cast<Asm::Args::Register32>(args[0]).name(), std::any_cast<Asm::Args::Mem32Ptr64>(args[1]).reg());
+
+ } else if (args[0].type() == typeid(Asm::Args::Register64) && args[1].type() == typeid(Asm::Args::Mem64Ptr64)) { // or reg64, [reg64]
+  machine_code = REX("W") + std::vector<uint8_t>{ 0x0B } + ModRM(std::any_cast<Asm::Args::Register64>(args[0]).name(), std::any_cast<Asm::Args::Mem64Ptr64>(args[1]).reg());
+
+ } else if (args[0].type() == typeid(Asm::Args::Mem32Ptr64) && args[1].type() == typeid(Asm::Args::Register32)) { // or [reg64], reg32
+  machine_code = std::vector<uint8_t>{ 0x09 } + ModRM(std::any_cast<Asm::Args::Register32>(args[1]).name(), std::any_cast<Asm::Args::Mem32Ptr64>(args[0]).reg());
+
+ } else if (args[0].type() == typeid(Asm::Args::Mem64Ptr64) && args[1].type() == typeid(Asm::Args::Register64)) { // or [reg64], reg64
+  machine_code = REX("W") + std::vector<uint8_t>{ 0x09 } + ModRM(std::any_cast<Asm::Args::Register64>(args[1]).name(), std::any_cast<Asm::Args::Mem64Ptr64>(args[0]).reg());
+
+ } else if (args[0].type() == typeid(Asm::Args::Register64) && args[1].type() == typeid(Asm::Args::Immediate32)) { // or reg64, imm32 (sign-extended)
+  machine_code = REX("W") + std::vector<uint8_t>{ 0x81 } + ModRM("/1", std::any_cast<Asm::Args::Register64>(args[0]).name()) + std::any_cast<Asm::Args::Immediate32>(args[1]).getCode();
+
+ } else {
+  throw std::runtime_error("Unimplemented: or "s + args[0].type().name() + " "s + args[1].type().name());
+ }
+}
+
+namespace {
+
+bool registered {
+ registerOp(mangleName<Asm::Args::Register8, Asm::Args::Register8>("or"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_or>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Register32, Asm::Args::Register32>("or"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_or>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Register64, Asm::Args::Register64>("or"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_or>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Register32, Asm::Args::Immediate32>("or"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_or>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Register32, Asm::Args::Mem32Ptr64>("or"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_or>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Mem32Ptr64, Asm::Args::Register32>("or"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_or>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Register64, Asm::Args::Mem64Ptr64>("or"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_or>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Mem64Ptr64, Asm::Args::Register64>("or"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_or>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Register64, Asm::Args::Immediate32>("or"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_or>(args);
+            })
+};
+
+}
diff --git a/asm/intel64/or.h b/asm/intel64/or.h
new file mode 100644
index 0000000..3362634
--- /dev/null
+++ b/asm/intel64/or.h
@@ -0,0 +1,31 @@
+// OR
+
+#pragma once
+
+#include <asm/assembler.h>
+
+class Op_or: public Op
+{
+public:
+ Op_or(const Asm::Args& args);
+
+public:
+ std::vector<uint8_t> getCode() override
+ {
+  return machine_code;
+ }
+
+ size_t size() override
+ {
+  return machine_code.size();
+ }
+
+ bool optimize() override ///< returns true if changed
+ {
+  return false;
+ }
+
+protected:
+ std::vector<uint8_t> machine_code;
+};
+
-- 
cgit v1.2.3