From 541a2dffdcb02063f71d21af22aebbd293c9e49f Mon Sep 17 00:00:00 2001 From: Roland Reichwein Date: Fri, 27 Nov 2020 22:51:50 +0100 Subject: Added CMP --- asm/intel64/all_ops.h | 1 + asm/intel64/cmp.cpp | 114 +++++++++++++++++++++++++++++++++++++++++++++++++ asm/intel64/cmp.h | 31 ++++++++++++++ asm/intel64/encode.cpp | 1 + 4 files changed, 147 insertions(+) create mode 100644 asm/intel64/cmp.cpp create mode 100644 asm/intel64/cmp.h (limited to 'asm') diff --git a/asm/intel64/all_ops.h b/asm/intel64/all_ops.h index 89313b2..f9dc05b 100644 --- a/asm/intel64/all_ops.h +++ b/asm/intel64/all_ops.h @@ -4,6 +4,7 @@ #include "and.h" #include "bsf.h" #include "bsr.h" +#include "cmp.h" #include "dec.h" #include "div.h" #include "idiv.h" diff --git a/asm/intel64/cmp.cpp b/asm/intel64/cmp.cpp new file mode 100644 index 0000000..3a2a582 --- /dev/null +++ b/asm/intel64/cmp.cpp @@ -0,0 +1,114 @@ +#include "cmp.h" + +#include "codes.h" + +#include +#include + +using namespace std::string_literals; + +Op_cmp::Op_cmp(const Asm::Args& args) +{ + if (args[0].type() == typeid(Asm::Args::Register32) && + std::any_cast(args[0]).name() == "eax" && + args[1].type() == typeid(Asm::Args::Immediate32)) + { // cmp eax, imm32 (before "cmp reg32, imm32"! It's shorter.) + machine_code = std::vector{ 0x3D } + std::any_cast(args[1]).getCode(); + + } else if (args[0].type() == typeid(Asm::Args::Register32) && + args[1].type() == typeid(Asm::Args::Immediate32)) + { // cmp reg32, imm32 + machine_code = std::vector{ 0x81 } + ModRM("/7", std::any_cast(args[0]).name()) + std::any_cast(args[1]).getCode(); + + } else if (args[0].type() == typeid(Asm::Args::Register64) && + std::any_cast(args[0]).name() == "rax" && + args[1].type() == typeid(Asm::Args::Immediate32)) + + { // cmp rax, imm32 (sign extended) + machine_code = REX("W") + std::vector{ 0x3D } + std::any_cast(args[1]).getCode(); + + } else if (args[0].type() == typeid(Asm::Args::Register8) && args[1].type() == typeid(Asm::Args::Register8)) { // cmp reg8, reg8 + machine_code = std::vector{ 0x38 } + ModRM(std::any_cast(args[1]).name(), std::any_cast(args[0]).name()); + + } else if (args[0].type() == typeid(Asm::Args::Register16) && args[1].type() == typeid(Asm::Args::Register16)) { // cmp reg16, reg16 + machine_code = OpSizePrefix() + std::vector{ 0x39 } + ModRM(std::any_cast(args[1]).name(), std::any_cast(args[0]).name()); + + } else if (args[0].type() == typeid(Asm::Args::Register32) && args[1].type() == typeid(Asm::Args::Register32)) { // cmp reg32, reg32 + machine_code = std::vector{ 0x39 } + ModRM(std::any_cast(args[1]).name(), std::any_cast(args[0]).name()); + + } else if (args[0].type() == typeid(Asm::Args::Register64) && args[1].type() == typeid(Asm::Args::Register64)) { // cmp reg64, reg64 + machine_code = REX("W") + std::vector{ 0x39 } + ModRM(std::any_cast(args[1]).name(), std::any_cast(args[0]).name()); + + } else if (args[0].type() == typeid(Asm::Args::Register32) && args[1].type() == typeid(Asm::Args::Mem32Ptr64)) { // cmp reg32, [reg64] + Asm::Args::Mem32Ptr64 ptr{std::any_cast(args[1])}; + machine_code = std::vector{ 0x3B } + ModRM(std::any_cast(args[0]).name(), ptr.reg(), ptr.offs()); + + } else if (args[0].type() == typeid(Asm::Args::Register64) && args[1].type() == typeid(Asm::Args::Mem64Ptr64)) { // cmp reg64, [reg64] + Asm::Args::Mem64Ptr64 ptr{std::any_cast(args[1])}; + machine_code = REX("W") + std::vector{ 0x3B } + ModRM(std::any_cast(args[0]).name(), ptr.reg(), ptr.offs()); + + } else if (args[0].type() == typeid(Asm::Args::Mem8Ptr64) && args[1].type() == typeid(Asm::Args::Immediate8)) { // cmp [reg64], imm8 + Asm::Args::Mem8Ptr64 ptr{std::any_cast(args[0])}; + machine_code = std::vector{ 0x80 } + ModRM("/7", ptr.reg(), ptr.offs()) + std::any_cast(args[1]).getCode(); + + } else if (args[0].type() == typeid(Asm::Args::Mem32Ptr64) && args[1].type() == typeid(Asm::Args::Immediate32)) { // cmp [reg64], imm32 + Asm::Args::Mem32Ptr64 ptr{std::any_cast(args[0])}; + machine_code = std::vector{ 0x81 } + ModRM("/7", ptr.reg(), ptr.offs()) + std::any_cast(args[1]).getCode(); + + } else if (args[0].type() == typeid(Asm::Args::Mem64Ptr64) && args[1].type() == typeid(Asm::Args::Immediate32)) { // cmp qword ptr [reg64], imm32 (sign-extended) + Asm::Args::Mem64Ptr64 ptr{std::any_cast(args[0])}; + machine_code = REX("W") + std::vector{ 0x81 } + ModRM("/7", ptr.reg(), ptr.offs()) + std::any_cast(args[1]).getCode(); + + } else if (args[0].type() == typeid(Asm::Args::Mem64Ptr64) && args[1].type() == typeid(Asm::Args::Immediate64)) { // cmp qword ptr [reg64], imm32 (sign-extended) - reduce imm64 to imm32! + Asm::Args::Mem64Ptr64 ptr{std::any_cast(args[0])}; + Asm::Args::Immediate32 imm32{std::any_cast(args[1])}; + machine_code = REX("W") + std::vector{ 0x81 } + ModRM("/7", ptr.reg(), ptr.offs()) + imm32.getCode(); + + } else { + throw std::runtime_error("Unimplemented: cmp "s + args[0].type().name() + " "s + args[1].type().name()); + } +} + +namespace { + +bool registered { + registerOp(mangleName("cmp"), [](const Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(args); + }) && + registerOp(mangleName("cmp"), [](const Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(args); + }) && + registerOp(mangleName("cmp"), [](const Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(args); + }) && + registerOp(mangleName("cmp"), [](const Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(args); + }) && + registerOp(mangleName("cmp"), [](const Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(args); + }) && + registerOp(mangleName("cmp"), [](const Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(args); + }) && + registerOp(mangleName("cmp"), [](const Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(args); + }) && + registerOp(mangleName("cmp"), [](const Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(args); + }) && + registerOp(mangleName("cmp"), [](const Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(args); + }) && + registerOp(mangleName("cmp"), [](const Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(args); + }) && + registerOp(mangleName("cmp"), [](const Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(args); + }) && + registerOp(mangleName("cmp"), [](const Asm::Args& args) -> std::shared_ptr{ // automatically converted to 32-bit (sign extended) if small enough. Intel doesn't support CMP ..., imm64 + return std::make_shared(args); + }) +}; + +} + diff --git a/asm/intel64/cmp.h b/asm/intel64/cmp.h new file mode 100644 index 0000000..7cad008 --- /dev/null +++ b/asm/intel64/cmp.h @@ -0,0 +1,31 @@ +// Compare Two Operands + +#pragma once + +#include + +class Op_cmp: public Op +{ +public: + Op_cmp(const Asm::Args& args); + +public: + std::vector getCode() override + { + return machine_code; + } + + size_t size() override + { + return machine_code.size(); + } + + bool optimize() override ///< returns true if changed + { + return false; + } + +protected: + std::vector machine_code; +}; + diff --git a/asm/intel64/encode.cpp b/asm/intel64/encode.cpp index 0d7eacb..388639d 100644 --- a/asm/intel64/encode.cpp +++ b/asm/intel64/encode.cpp @@ -225,6 +225,7 @@ void Asm::toMachineCode(const FlowGraph::Graph& graph, Segment& segment) segment.push_back(makeStoreValue(operands[0], graph)); } else if (op.type() == FlowGraph::UnaryOperationType::LogicalNot) { segment.push_back(makeLoadValue(operands[1], graph)); + // TODO: cmp eax, 0 \n sete al \n movsx eax, al segment.append(parseAsm("bsr eax")); // ZF=1 iff eax=0 segment.append(parseAsm("lahf")); // ZF in AH bit 6 segment.append(parseAsm("shr eax, 14")); // ZF in eax bit 0 -- cgit v1.2.3