From 7edbd99775416a32c88acf8e9379518436905f02 Mon Sep 17 00:00:00 2001 From: Roland Reichwein Date: Sat, 21 Nov 2020 15:19:45 +0100 Subject: Support gcc 10 and clang 11 --- asm/intel64/div.cpp | 18 ++++++++++++++++++ asm/intel64/encode.cpp | 41 +++++++++++++++++++++++++++++++++++++++++ asm/intel64/mul.cpp | 18 ++++++++++++++++++ asm/parse.cpp | 7 +++++++ 4 files changed, 84 insertions(+) (limited to 'asm') diff --git a/asm/intel64/div.cpp b/asm/intel64/div.cpp index 9ca24e9..1e98b7b 100644 --- a/asm/intel64/div.cpp +++ b/asm/intel64/div.cpp @@ -20,6 +20,15 @@ Op_div::Op_div(const Asm::Args& args) } else if (args[0].type() == typeid(Asm::Args::Register64)) { // div reg64 (accu is rax (remainder=rdx) <- rdx:rax / reg64) machine_code = REX("W") + std::vector{ 0xF7 } + ModRM("/6", std::any_cast(args[0]).name()); + } else if (args[0].type() == typeid(Asm::Args::Mem8Ptr64)) { // div byte ptr [reg64] (accu is al (remainder=ah) <- ah / x) + machine_code = std::vector{ 0xF6 } + + ModRM("/6", std::any_cast(args[0]).reg()); + } else if (args[0].type() == typeid(Asm::Args::Mem32Ptr64)) { // div dword ptr [reg64] (accu is eax (remainder=edx) <- edx:eax / x) + machine_code = std::vector{ 0xF7 } + + ModRM("/6", std::any_cast(args[0]).reg()); + } else if (args[0].type() == typeid(Asm::Args::Mem64Ptr64)) { // div qword ptr [reg64] (accu is rax (remainder=rdx) <- rdx:rax / x) + machine_code = REX("W") + std::vector{ 0xF7 } + + ModRM("/6", std::any_cast(args[0]).reg()); } else { throw std::runtime_error("Unimplemented: div "s + args[0].type().name()); } @@ -36,6 +45,15 @@ bool registered { }) && registerOp(mangleName("div"), [](const Asm::Args& args) -> std::shared_ptr{ return std::make_shared(args); + }) && + registerOp(mangleName("div"), [](const Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(args); + }) && + registerOp(mangleName("div"), [](const Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(args); + }) && + registerOp(mangleName("div"), [](const Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(args); }) }; diff --git a/asm/intel64/encode.cpp b/asm/intel64/encode.cpp index 1b35d89..a2434fd 100644 --- a/asm/intel64/encode.cpp +++ b/asm/intel64/encode.cpp @@ -114,6 +114,36 @@ std::vector> makeMulValue(const FlowGraph::Data& data, co throw std::runtime_error("ICE: Unsupported type for operand data at mul: "s + demangle(typeid(data_storage))); } +std::vector> makeDivValue(const FlowGraph::Data& data, const FlowGraph::Graph& graph) +{ + if (data.type() != FlowGraph::DataType::Int) { + throw std::runtime_error("Bad type for operand: "s + std::to_string(int(data.type()))); + } + + if (!data.storage()) + throw std::runtime_error("ICE: Operand storage is 0"); + + auto& data_storage{*data.storage()}; + if (typeid(data_storage) == typeid(FlowGraph::Constant)) { + FlowGraph::Constant& value {dynamic_cast(data_storage)}; + if (value.value().size() < sizeof(uint32_t)) + throw std::runtime_error("ICE: Int data from operand needs at least 4 bytes, got "s + std::to_string(value.value().size())); + + uint32_t immediate = from_little_endian(value.value()); + + return {{ + makeOp("mov", Asm::Args{{Asm::Args::Register32("ebx"), Asm::Args::Immediate32(immediate)}}), + makeOp("div", Asm::Args{{Asm::Args::Register32("ebx")}}) + }}; + } else if (typeid(data_storage) == typeid(FlowGraph::TemporaryStorage)) { + //FlowGraph::TemporaryStorage& storage {dynamic_cast(data_storage)}; + + index_t index { graph.scope()->indexOfData(data)}; + return {{makeOp("div", Asm::Args{{Asm::Args::Mem32Ptr64("rbp", int32_t(index) * -4)}})}}; + } else + throw std::runtime_error("ICE: Unsupported type for operand data at div: "s + demangle(typeid(data_storage))); +} + } // namespace void Asm::toMachineCode(const FlowGraph::Graph& graph, Segment& segment) @@ -165,6 +195,17 @@ void Asm::toMachineCode(const FlowGraph::Graph& graph, Segment& segment) segment.push_back(makeLoadValue(operands[1], graph)); segment.append(makeMulValue(operands[2], graph)); segment.push_back(makeStoreValue(operands[0], graph)); + } else if (op.type() == FlowGraph::BinaryOperationType::Divide) { + segment.push_back(makeLoadValue(operands[1], graph)); + segment.append(parseAsm("xor edx, edx")); + segment.append(makeDivValue(operands[2], graph)); + segment.push_back(makeStoreValue(operands[0], graph)); + } else if (op.type() == FlowGraph::BinaryOperationType::Modulo) { + segment.push_back(makeLoadValue(operands[1], graph)); + segment.append(parseAsm("xor edx, edx")); + segment.append(makeDivValue(operands[2], graph)); + segment.append(parseAsm("mov eax, edx")); // remainder is in edx + segment.push_back(makeStoreValue(operands[0], graph)); } else throw std::runtime_error("ICE: Asm: Unsupported binary operation type: "s + std::to_string(static_cast(op.type()))); diff --git a/asm/intel64/mul.cpp b/asm/intel64/mul.cpp index 502b1d9..5825e2a 100644 --- a/asm/intel64/mul.cpp +++ b/asm/intel64/mul.cpp @@ -20,6 +20,15 @@ Op_mul::Op_mul(const Asm::Args& args) } else if (args[0].type() == typeid(Asm::Args::Register64)) { // mul reg64 (accu is rdx:rax <- rax) machine_code = REX("W") + std::vector{ 0xF7 } + ModRM("/4", std::any_cast(args[0]).name()); + } else if (args[0].type() == typeid(Asm::Args::Mem8Ptr64)) { // mul byte ptr [reg64] (accu is ax <- al) + machine_code = std::vector{ 0xF6 } + + ModRM("/4", std::any_cast(args[0]).reg()); + } else if (args[0].type() == typeid(Asm::Args::Mem32Ptr64)) { // mul dword ptr [reg64] (accu is edx:eax <- eax) + machine_code = std::vector{ 0xF7 } + + ModRM("/4", std::any_cast(args[0]).reg()); + } else if (args[0].type() == typeid(Asm::Args::Mem64Ptr64)) { // mul qword ptr [reg64] (accu is rdx:rax <- rax) + machine_code = REX("W") + std::vector{ 0xF7 } + + ModRM("/4", std::any_cast(args[0]).reg()); } else { throw std::runtime_error("Unimplemented: mul "s + args[0].type().name()); } @@ -36,6 +45,15 @@ bool registered { }) && registerOp(mangleName("mul"), [](const Asm::Args& args) -> std::shared_ptr{ return std::make_shared(args); + }) && + registerOp(mangleName("mul"), [](const Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(args); + }) && + registerOp(mangleName("mul"), [](const Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(args); + }) && + registerOp(mangleName("mul"), [](const Asm::Args& args) -> std::shared_ptr{ + return std::make_shared(args); }) }; diff --git a/asm/parse.cpp b/asm/parse.cpp index 8f6f831..28e79f3 100644 --- a/asm/parse.cpp +++ b/asm/parse.cpp @@ -20,6 +20,13 @@ namespace { "dl", "dh", }; + std::unordered_set reg16 { + "ax", "sp", + "bx", "bp", + "cx", "si", + "dx", "di", + }; + std::unordered_set reg32 { "eax", "esp", "ebx", "ebp", -- cgit v1.2.3