From 8f28495ab9a8ebf53868405541e907394895e51f Mon Sep 17 00:00:00 2001 From: Roland Reichwein Date: Sat, 17 Oct 2020 21:45:37 +0200 Subject: Add add --- asm/assembler.h | 38 ++++++++++++++++++++++++++++++++++++++ asm/intel64/add.cpp | 31 +++++++++++++++++++++++++++++++ asm/intel64/add.h | 31 +++++++++++++++++++++++++++++++ asm/intel64/codes.cpp | 17 +++++++++++++++++ asm/intel64/codes.h | 8 ++++++++ 5 files changed, 125 insertions(+) create mode 100644 asm/intel64/add.cpp create mode 100644 asm/intel64/add.h create mode 100644 asm/intel64/codes.cpp create mode 100644 asm/intel64/codes.h (limited to 'asm') diff --git a/asm/assembler.h b/asm/assembler.h index ddea4af..3d3e9a9 100644 --- a/asm/assembler.h +++ b/asm/assembler.h @@ -2,6 +2,8 @@ #include "chunk.h" +#include + #include #include #include @@ -47,8 +49,44 @@ class Immediate8 public: Immediate8(uint8_t value): m_value(value) {} uint8_t value() {return m_value;} + std::vector getCode() {return {m_value};}; private: uint8_t m_value; }; +class Immediate32 +{ +public: + Immediate32(uint32_t value): m_value(value) {} + uint32_t value() { return m_value; } + std::vector getCode() { + std::vector result(size_t(4)); + *(reinterpret_cast(result.data())) = boost::endian::native_to_little(m_value); + return result; + }; + +private: + uint32_t m_value; +}; + +class Register32 +{ +public: + Register32(const std::string& name): m_name(name) {} + std::string name() { return m_name; } + +private: + std::string m_name; +}; + +class Register64 +{ +public: + Register64(const std::string& name): m_name(name) {} + std::string name() { return m_name; } + +private: + std::string m_name; +}; + diff --git a/asm/intel64/add.cpp b/asm/intel64/add.cpp new file mode 100644 index 0000000..dc5c704 --- /dev/null +++ b/asm/intel64/add.cpp @@ -0,0 +1,31 @@ +#include "add.h" + +#include "codes.h" + +#include +#include + +using namespace std::string_literals; + +Op_add::Op_add(AsmArgs& args) +{ + if (args[0].type() == typeid(Register32) && std::any_cast(args[0]).name() == "eax" && args[1].type() == typeid(Immediate32)) { // add eax, imm32 + machine_code = std::vector{ 0x05 } + std::any_cast(args[1]).getCode(); + } else if (args[0].type() == typeid(Register64) && std::any_cast(args[0]).name() == "rax" && args[1].type() == typeid(Immediate32)) { // add rax, imm32 + machine_code = REX("W") + std::vector{ 0x05 } + std::any_cast(args[1]).getCode(); + } else { + throw std::runtime_error("Unimplemented: add "s + args[0].type().name() + " "s + args[1].type().name()); + } +} + +namespace { + +bool registered0 { registerOp(mangleName("add"), [](AsmArgs& args) -> std::shared_ptr{ + return std::make_shared(args); + }) }; +// TODO +bool registered1 { registerOp(mangleName("add"), [](AsmArgs& args) -> std::shared_ptr{ + return std::make_shared(args); + }) }; + +} diff --git a/asm/intel64/add.h b/asm/intel64/add.h new file mode 100644 index 0000000..4c6b589 --- /dev/null +++ b/asm/intel64/add.h @@ -0,0 +1,31 @@ +// Integer Addition + +#pragma once + +#include + +class Op_add: public Op +{ +public: + Op_add(AsmArgs& args); + +public: + std::vector getCode() override + { + return machine_code; + } + + size_t size() override + { + return machine_code.size(); + } + + bool optimize() override ///< returns true if changed + { + return false; + } + +protected: + std::vector machine_code; +}; + diff --git a/asm/intel64/codes.cpp b/asm/intel64/codes.cpp new file mode 100644 index 0000000..a1d9e87 --- /dev/null +++ b/asm/intel64/codes.cpp @@ -0,0 +1,17 @@ +#include "codes.h" + +// REX prefix: 0b0100WRXB +std::vector REX(std::string s) { + uint8_t result{0b01000000}; + if (s == "W") + result |= 0b00001000; + if (s == "R") + result |= 0b00000100; + if (s == "X") + result |= 0b00000010; + if (s == "B") + result |= 0b00000001; + + return { result }; +} + diff --git a/asm/intel64/codes.h b/asm/intel64/codes.h new file mode 100644 index 0000000..32eff1c --- /dev/null +++ b/asm/intel64/codes.h @@ -0,0 +1,8 @@ +#pragma once + +#include +#include +#include + +// REX prefix: 0b0100WRXB +std::vector REX(std::string s); -- cgit v1.2.3