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authorRoland Reichwein <mail@reichwein.it>2020-11-28 12:08:10 +0100
committerRoland Reichwein <mail@reichwein.it>2020-11-28 12:08:10 +0100
commit108569319d85a1832700f70ae6c93d7e926dfa92 (patch)
tree497d1db278ca65c65afaf03ec8c3a93f8f1a3a09
parentf82ed28acbbbf10a243e44dcbc4ddeebc0dde446 (diff)
Implemented SETcc - Set Byte On Condition
-rw-r--r--Makefile1
-rw-r--r--asm/intel64/all_ops.h1
-rw-r--r--asm/intel64/setcc.cpp84
-rw-r--r--asm/intel64/setcc.h31
4 files changed, 117 insertions, 0 deletions
diff --git a/Makefile b/Makefile
index f1bb23a..5394354 100644
--- a/Makefile
+++ b/Makefile
@@ -74,6 +74,7 @@ PROGSRC=\
asm/intel64/ror.cpp \
asm/intel64/sal_shl.cpp \
asm/intel64/sar.cpp \
+ asm/intel64/setcc.cpp \
asm/intel64/shr.cpp \
asm/intel64/sub.cpp \
asm/intel64/trivials.cpp \
diff --git a/asm/intel64/all_ops.h b/asm/intel64/all_ops.h
index a64ae81..75b28f9 100644
--- a/asm/intel64/all_ops.h
+++ b/asm/intel64/all_ops.h
@@ -26,6 +26,7 @@
#include "ror.h"
#include "sal_shl.h"
#include "sar.h"
+#include "setcc.h"
#include "shr.h"
#include "sub.h"
#include "trivials.h"
diff --git a/asm/intel64/setcc.cpp b/asm/intel64/setcc.cpp
new file mode 100644
index 0000000..aa7219f
--- /dev/null
+++ b/asm/intel64/setcc.cpp
@@ -0,0 +1,84 @@
+#include "setcc.h"
+
+#include "codes.h"
+
+#include <asm/assembler.h>
+#include <asm/operators.h>
+
+#include <asm/intel64/codes.h>
+
+using namespace std::string_literals;
+
+namespace {
+ struct Operation {
+ std::string name;
+ OP_T opcode;
+ };
+
+ std::vector<Operation> setccOps {
+ {"seta", OP_T{ 0x0F, 0x97 }},
+ {"setae", OP_T{ 0x0F, 0x93 }},
+ {"setb", OP_T{ 0x0F, 0x92 }},
+ {"setbe", OP_T{ 0x0F, 0x96 }},
+ {"setc", OP_T{ 0x0F, 0x92 }},
+ {"sete", OP_T{ 0x0F, 0x94 }},
+ {"setg", OP_T{ 0x0F, 0x9F }},
+ {"setge", OP_T{ 0x0F, 0x9D }},
+ {"setl", OP_T{ 0x0F, 0x9C }},
+ {"setle", OP_T{ 0x0F, 0x9E }},
+ {"setna", OP_T{ 0x0F, 0x96 }},
+ {"setnae",OP_T{ 0x0F, 0x92 }},
+ {"setnb", OP_T{ 0x0F, 0x93 }},
+ {"setnbe",OP_T{ 0x0F, 0x97 }},
+ {"setnc", OP_T{ 0x0F, 0x93 }},
+ {"setne", OP_T{ 0x0F, 0x95 }},
+ {"setng", OP_T{ 0x0F, 0x9E }},
+ {"setnge",OP_T{ 0x0F, 0x9C }},
+ {"setnl", OP_T{ 0x0F, 0x9D }},
+ {"setnle",OP_T{ 0x0F, 0x9F }},
+ {"setno", OP_T{ 0x0F, 0x91 }},
+ {"setnp", OP_T{ 0x0F, 0x9B }},
+ {"setns", OP_T{ 0x0F, 0x99 }},
+ {"setnz", OP_T{ 0x0F, 0x95 }},
+ {"seto", OP_T{ 0x0F, 0x90 }},
+ {"setp", OP_T{ 0x0F, 0x9A }},
+ {"setpe", OP_T{ 0x0F, 0x9A }},
+ {"setpo", OP_T{ 0x0F, 0x9B }},
+ {"sets", OP_T{ 0x0F, 0x98 }},
+ {"setz", OP_T{ 0x0F, 0x94 }},
+ };
+
+ bool registerOps() {
+ bool result{true};
+ for (const auto& setccOp: setccOps) {
+ result &= registerOp(mangleName<Asm::Args::Register8>(setccOp.name), [&](const Asm::Args& args) -> std::shared_ptr<Op>{
+ return std::make_shared<Op_setcc>(setccOp.name, args, setccOp.opcode);
+ });
+ result &= registerOp(mangleName<Asm::Args::Mem8Ptr64>(setccOp.name), [&](const Asm::Args& args) -> std::shared_ptr<Op>{
+ return std::make_shared<Op_setcc>(setccOp.name, args, setccOp.opcode);
+ });
+ }
+ return result;
+ }
+
+ bool registered {
+ registerOps()
+ };
+}
+
+Op_setcc::Op_setcc(const std::string& name, const Asm::Args& args, const OP_T& opcode)
+{
+ if (args[0].type() == typeid(Asm::Args::Register8)) { // setcc reg8
+ // actually, reg field of ModRM is ignored and could be different from /0
+ machine_code = opcode + ModRM("/0", std::any_cast<Asm::Args::Register8>(args[0]).name());
+
+ } else if (args[0].type() == typeid(Asm::Args::Mem8Ptr64)) { // setcc byte ptr [reg64]
+ Asm::Args::Mem8Ptr64 ptr{std::any_cast<Asm::Args::Mem8Ptr64>(args[0])};
+ // actually, reg field of ModRM is ignored and could be different from /0
+ machine_code = opcode + ModRM("/0", ptr.reg(), ptr.offs());
+
+ } else {
+ throw std::runtime_error("Unimplemented: setcc "s + args[0].type().name() + " "s + args[1].type().name());
+ }
+}
+
diff --git a/asm/intel64/setcc.h b/asm/intel64/setcc.h
new file mode 100644
index 0000000..1bd0d3f
--- /dev/null
+++ b/asm/intel64/setcc.h
@@ -0,0 +1,31 @@
+// SETcc - Set Byte On Condition
+
+#pragma once
+
+#include <asm/assembler.h>
+
+class Op_setcc: public Op
+{
+public:
+ Op_setcc(const std::string& name, const Asm::Args& args, const OP_T& opcode);
+
+public:
+ std::vector<uint8_t> getCode() override
+ {
+ return machine_code;
+ }
+
+ size_t size() override
+ {
+ return machine_code.size();
+ }
+
+ bool optimize() override ///< returns true if changed
+ {
+ return false;
+ }
+
+protected:
+ std::vector<uint8_t> machine_code;
+};
+