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authorRoland Reichwein <mail@reichwein.it>2020-11-18 17:55:27 +0100
committerRoland Reichwein <mail@reichwein.it>2020-11-18 17:55:27 +0100
commit031bfef600e7021c8bd72e2e663f368e7386b131 (patch)
tree4e724c3b13278e5c6fb90a9380d19dc1d253b4b3 /Makefile
parent927eb99e75325164a541c2638e1e607294019381 (diff)
Added Asm ops
Diffstat (limited to 'Makefile')
-rw-r--r--Makefile13
1 files changed, 13 insertions, 0 deletions
diff --git a/Makefile b/Makefile
index 1ef9a12..c2d1850 100644
--- a/Makefile
+++ b/Makefile
@@ -48,6 +48,9 @@ PROGSRC=\
asm/assembler.cpp \
asm/chunk.cpp \
asm/intel64/add.cpp \
+ asm/intel64/and.cpp \
+ asm/intel64/bsf.cpp \
+ asm/intel64/bsr.cpp \
asm/intel64/dec.cpp \
asm/intel64/div.cpp \
asm/intel64/idiv.cpp \
@@ -57,14 +60,24 @@ PROGSRC=\
asm/intel64/jmp.cpp \
asm/intel64/mov.cpp \
asm/intel64/mul.cpp \
+ asm/intel64/neg.cpp \
+ asm/intel64/not.cpp \
asm/intel64/pop.cpp \
asm/intel64/push.cpp \
+ asm/intel64/rcl.cpp \
+ asm/intel64/rcr.cpp \
+ asm/intel64/rol.cpp \
+ asm/intel64/ror.cpp \
+ asm/intel64/sal_shl.cpp \
+ asm/intel64/sar.cpp \
+ asm/intel64/shr.cpp \
asm/intel64/sub.cpp \
asm/intel64/trivials.cpp \
asm/intel64/xor.cpp \
asm/intel64/codes.cpp \
asm/intel64/encode.cpp \
asm/operators.cpp \
+ asm/parse.cpp \
asm/segment.cpp \
bnf.cpp \
cpp.cpp \