Added insns

1 files changed, 19 insertions, 0 deletions

diff --git a/asm/arm/instruction.h b/asm/arm/instruction.h
index 0aeb5eb..d6c8b12 100644
--- a/asm/arm/instruction.h
+++ b/asm/arm/instruction.h
@@ -123,12 +123,21 @@ namespace {
  std::shared_ptr<Operand> cond(uint8_t pos) { throw std::runtime_error("Unimplemented: cond"); }
 
  std::shared_ptr<Operand> suffixed(std::shared_ptr<Operand> op) { throw std::runtime_error("Unimplemented: suffixed"); }
+ // suffixes: list of alternative suffixes as strings, including ""
  template<typename T, typename... Targs>
  std::shared_ptr<Operand> suffixed(std::shared_ptr<Operand> op, T suffix, Targs... suffixes) {
   // TODO: add suffix to op
   return suffixed(op, suffixes...);
  }
 
+ std::shared_ptr<Operand> prefixed(std::shared_ptr<Operand> op) { throw std::runtime_error("Unimplemented: prefixed"); }
+ // prefixes: list of alternative refixes as strings, including ""
+ template<typename T, typename... Targs>
+ std::shared_ptr<Operand> prefixed(std::shared_ptr<Operand> op, T prefix, Targs... prefixes) {
+  // TODO: add prefix to op
+  return prefixed(op, prefixes...);
+ }
+
  std::shared_ptr<Operand> bracketed(Operands operands) { throw std::runtime_error("Unimplemented: bracketed"); };
  std::shared_ptr<Operand> optional(std::shared_ptr<Operand> op) { return op; }
 
@@ -190,6 +199,16 @@ namespace {
   {"movs", 2, Pattern(0x2000, high_bits(5)), Operands{reg(3, 0), imm(8, 0)}}, // T1
   {"mov", 2, Pattern(0x4600, high_bits(8)), Operands{reg(0x87), reg(4, 3)}}, // T1
   {"movs", 2, Pattern(0x0000, high_bits(10)), Operands{reg(3, 0), reg(3, 3)}}, // T2
+  {"movs", 2, Pattern(0x1000, high_bits(5)).alternative_syntax(), Operands{reg(3, 0), reg(3, 3), prefixed(imm(5, 6, 1, 32), "asr ")}}, // T1
+  {"movs", 2, Pattern(0x0000, high_bits(5)).alternative_syntax(), Operands{reg(3, 0), reg(3, 3), prefixed(imm(5, 6, 1, 0, {0}), "lsl ")}}, // T1
+  {"movs", 2, Pattern(0x0800, high_bits(5)).alternative_syntax(), Operands{reg(3, 0), reg(3, 3), prefixed(imm(5, 6, 1, 0, {0}), "lsr ")}}, // T1
+  {"movs", 2, Pattern(0x4100, high_bits(10)).alternative_syntax(), Operands{same_reg(1), reg(3, 0), prefixed(reg(3, 3), "asr ")}}, // T1
+  {"movs", 2, Pattern(0x4080, high_bits(10)).alternative_syntax(), Operands{reg(3, 0), same_reg(0), prefixed(reg(3, 3), "lsl ")}}, // T1
+  {"movs", 2, Pattern(0x40C0, high_bits(10)).alternative_syntax(), Operands{reg(3, 0), same_reg(0), prefixed(reg(3, 3), "lsr ")}}, // T1
+  {"movs", 2, Pattern(0x41C0, high_bits(10)).alternative_syntax(), Operands{reg(3, 0), same_reg(0), prefixed(reg(3, 3), "ror ")}}, // T1
+  //{"mrs", 2,
+
+  {"rors", 2, Pattern(0x41C0, high_bits(10)), Operands{reg(3, 0), same_reg(0), reg(3, 3)}}, // T1
  };
 };