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authorRoland Reichwein <mail@reichwein.it>2020-11-09 09:50:58 +0100
committerRoland Reichwein <mail@reichwein.it>2020-11-09 09:50:58 +0100
commit1ac8ab06e9aad3b6d22685255459d71cb49e1f28 (patch)
tree95e4ca7de492180aef9d459ee40663b1bf134b66 /asm/intel64/add.cpp
parentdb0654fa48ddc07e6bcaaaeddfa301a32806dadc (diff)
First program: Can add 2 integers and return result via exit code
Diffstat (limited to 'asm/intel64/add.cpp')
-rw-r--r--asm/intel64/add.cpp6
1 files changed, 5 insertions, 1 deletions
diff --git a/asm/intel64/add.cpp b/asm/intel64/add.cpp
index 106ffec..4438895 100644
--- a/asm/intel64/add.cpp
+++ b/asm/intel64/add.cpp
@@ -12,8 +12,12 @@ Op_add::Op_add(Asm::Args& args)
if (args[0].type() == typeid(Asm::Args::Register32) &&
std::any_cast<Asm::Args::Register32>(args[0]).name() == "eax" &&
args[1].type() == typeid(Asm::Args::Immediate32))
- { // add eax, imm32
+ { // add eax, imm32 (before "add reg32, imm32"! It's shorter.)
machine_code = std::vector<uint8_t>{ 0x05 } + std::any_cast<Asm::Args::Immediate32>(args[1]).getCode();
+ } else if (args[0].type() == typeid(Asm::Args::Register32) &&
+ args[1].type() == typeid(Asm::Args::Immediate32))
+ { // add reg32, imm32
+ machine_code = std::vector<uint8_t>{ 0x81 } + ModRM("/0", std::any_cast<Asm::Args::Register32>(args[0]).name()) + std::any_cast<Asm::Args::Immediate32>(args[1]).getCode();
} else if (args[0].type() == typeid(Asm::Args::Register64) &&
std::any_cast<Asm::Args::Register64>(args[0]).name() == "rax" &&
args[1].type() == typeid(Asm::Args::Immediate32))