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authorRoland Reichwein <mail@reichwein.it>2020-11-22 13:00:06 +0100
committerRoland Reichwein <mail@reichwein.it>2020-11-22 13:00:06 +0100
commit1fae63de23320a1663b7c591e247ad81852ab6dc (patch)
treebfe539b7eeb5a4d7b68aa1bf853898d60e34f784 /asm/intel64/codes.cpp
parent739297d8895b08a9ecd8e81b01b7ba8e8dc4a8ae (diff)
Support 16-bit short
Diffstat (limited to 'asm/intel64/codes.cpp')
-rw-r--r--asm/intel64/codes.cpp9
1 files changed, 8 insertions, 1 deletions
diff --git a/asm/intel64/codes.cpp b/asm/intel64/codes.cpp
index 76108a1..18980bd 100644
--- a/asm/intel64/codes.cpp
+++ b/asm/intel64/codes.cpp
@@ -1,5 +1,6 @@
#include "codes.h"
+#include "byteorder.h"
#include "minicc.h"
#include "../operators.h"
@@ -84,7 +85,7 @@ std::vector<uint8_t> ModRM(const std::string& reg, const std::string& rm, int32_
displacement_bytes.push_back(uint8_t(disp));
} else {
result |= 0b10000000; // 32 bit displacement
- displacement_bytes += to_little_endian(disp);
+ displacement_bytes += endian::to_little(uint32_t(disp));
}
result |= rm_bits;
} else { // normal register access
@@ -104,6 +105,12 @@ uint8_t RegNo(const std::string& reg)
return index->second;
}
+// Switch from operand size 64bit to 32bit
+std::vector<uint8_t> OpSizePrefix()
+{
+ return {0x66};
+}
+
#if 0
prefixes{
"lock", 0xf0,