diff options
author | Roland Reichwein <mail@reichwein.it> | 2020-11-18 17:55:27 +0100 |
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committer | Roland Reichwein <mail@reichwein.it> | 2020-11-18 17:55:27 +0100 |
commit | 031bfef600e7021c8bd72e2e663f368e7386b131 (patch) | |
tree | 4e724c3b13278e5c6fb90a9380d19dc1d253b4b3 /asm/intel64/sal_shl.cpp | |
parent | 927eb99e75325164a541c2638e1e607294019381 (diff) |
Added Asm ops
Diffstat (limited to 'asm/intel64/sal_shl.cpp')
-rw-r--r-- | asm/intel64/sal_shl.cpp | 79 |
1 files changed, 79 insertions, 0 deletions
diff --git a/asm/intel64/sal_shl.cpp b/asm/intel64/sal_shl.cpp new file mode 100644 index 0000000..c822666 --- /dev/null +++ b/asm/intel64/sal_shl.cpp @@ -0,0 +1,79 @@ +#include "sal_shl.h" + +#include "codes.h" + +#include <asm/assembler.h> +#include <asm/operators.h> + +using namespace std::string_literals; + +Op_sal::Op_sal(const Asm::Args& args) +{ + if (args[1].type() == typeid(Asm::Args::Immediate8)) { + std::vector<uint8_t> shift_offset{std::any_cast<Asm::Args::Immediate8>(args[1]).getCode()}; + if (shift_offset == std::vector<uint8_t>{ 0x01 }) { // 1 bit version is shorter + if (args[0].type() == typeid(Asm::Args::Register8)) { // sal reg8, 1 + machine_code = std::vector<uint8_t>{ 0xD0 } + ModRM("/4", std::any_cast<Asm::Args::Register8>(args[0]).name()); + } else if (args[0].type() == typeid(Asm::Args::Register32)) { // sal reg32, 1 + machine_code = std::vector<uint8_t>{ 0xD1 } + ModRM("/4", std::any_cast<Asm::Args::Register8>(args[0]).name()); + } else if (args[0].type() == typeid(Asm::Args::Register64)) { // sal reg64, 1 + machine_code = REX("W") + std::vector<uint8_t>{ 0xD1 } + ModRM("/4", std::any_cast<Asm::Args::Register8>(args[0]).name()); + } + } else { // general version >= 2 bits shift + if (args[0].type() == typeid(Asm::Args::Register8)) { // sal reg8, imm8 + machine_code = std::vector<uint8_t>{ 0xC0 } + ModRM("/4", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset; + } else if (args[0].type() == typeid(Asm::Args::Register32)) { // sal reg32, imm8 + machine_code = std::vector<uint8_t>{ 0xC1 } + ModRM("/4", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset; + } else if (args[0].type() == typeid(Asm::Args::Register64)) { // sal reg64, imm8 + machine_code = REX("W") + std::vector<uint8_t>{ 0xC1 } + ModRM("/4", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset; + } + } + + } else { + throw std::runtime_error("Unimplemented: sal(shl) "s + args[0].type().name() + " "s + args[1].type().name()); + } +} + +namespace { + +bool registered { + registerOp(mangleName<Asm::Args::Register8, Asm::Args::Immediate8>("sal"), [](const Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_sal>(args); + }) && + registerOp(mangleName<Asm::Args::Register32, Asm::Args::Immediate8>("sal"), [](const Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_sal>(args); + }) && + registerOp(mangleName<Asm::Args::Register64, Asm::Args::Immediate8>("sal"), [](const Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_sal>(args); + }) && + registerOp(mangleName<Asm::Args::Mem8Ptr64, Asm::Args::Immediate8>("sal"), [](const Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_sal>(args); + }) && + registerOp(mangleName<Asm::Args::Mem32Ptr64, Asm::Args::Immediate8>("sal"), [](const Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_sal>(args); + }) && + registerOp(mangleName<Asm::Args::Mem64Ptr64, Asm::Args::Immediate8>("sal"), [](const Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_sal>(args); + }) && + registerOp(mangleName<Asm::Args::Register8, Asm::Args::Immediate8>("shl"), [](const Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_sal>(args); + }) && + registerOp(mangleName<Asm::Args::Register32, Asm::Args::Immediate8>("shl"), [](const Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_sal>(args); + }) && + registerOp(mangleName<Asm::Args::Register64, Asm::Args::Immediate8>("shl"), [](const Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_sal>(args); + }) && + registerOp(mangleName<Asm::Args::Mem8Ptr64, Asm::Args::Immediate8>("shl"), [](const Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_sal>(args); + }) && + registerOp(mangleName<Asm::Args::Mem32Ptr64, Asm::Args::Immediate8>("shl"), [](const Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_sal>(args); + }) && + registerOp(mangleName<Asm::Args::Mem64Ptr64, Asm::Args::Immediate8>("shl"), [](const Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_sal>(args); + }) +}; + +} + |