Added intel sub, div, idiv

7 files changed, 224 insertions, 0 deletions

diff --git a/asm/intel64/all_ops.h b/asm/intel64/all_ops.h
index 9f41c5d..82f518f 100644
--- a/asm/intel64/all_ops.h
+++ b/asm/intel64/all_ops.h
@@ -2,6 +2,8 @@
 
 #include "add.h"
 #include "dec.h"
+#include "div.h"
+#include "idiv.h"
 #include "imul.h"
 #include "inc.h"
 #include "int.h"
@@ -10,4 +12,5 @@
 #include "mul.h"
 #include "nop.h"
 #include "ret.h"
+#include "sub.h"
 #include "xor.h"
diff --git a/asm/intel64/div.cpp b/asm/intel64/div.cpp
new file mode 100644
index 0000000..5ed9988
--- /dev/null
+++ b/asm/intel64/div.cpp
@@ -0,0 +1,43 @@
+#include "div.h"
+
+#include "codes.h"
+
+#include <asm/assembler.h>
+#include <asm/operators.h>
+
+#include <asm/intel64/codes.h>
+
+using namespace std::string_literals;
+
+Op_div::Op_div(Asm::Args& args)
+{
+ if (args[0].type() == typeid(Asm::Args::Register8)) { // div reg8 (accu is al (remainder=ah) <- ah / reg8)
+  machine_code = std::vector<uint8_t>{ 0xF6 } +
+   ModRM("/6", std::any_cast<Asm::Args::Register8>(args[0]).name());
+ } else if (args[0].type() == typeid(Asm::Args::Register32)) { // div reg32 (accu is eax (remainder=edx) <- edx:eax / reg32)
+  machine_code = std::vector<uint8_t>{ 0xF7 } +
+   ModRM("/6", std::any_cast<Asm::Args::Register32>(args[0]).name());
+ } else if (args[0].type() == typeid(Asm::Args::Register64)) { // div reg64 (accu is rax (remainder=rdx) <- rdx:rax / reg64)
+  machine_code = REX("W") + std::vector<uint8_t>{ 0xF7 } +
+   ModRM("/6", std::any_cast<Asm::Args::Register64>(args[0]).name());
+ } else {
+  throw std::runtime_error("Unimplemented: div "s + args[0].type().name());
+ }
+}
+
+namespace {
+
+bool registered {
+ registerOp(mangleName<Asm::Args::Register8>("div"), [](Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_div>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Register32>("div"), [](Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_div>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Register64>("div"), [](Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_div>(args);
+            })
+};
+
+}
+
diff --git a/asm/intel64/div.h b/asm/intel64/div.h
new file mode 100644
index 0000000..9605f3e
--- /dev/null
+++ b/asm/intel64/div.h
@@ -0,0 +1,31 @@
+// Divide Unsigned Integer
+
+#pragma once
+
+#include <asm/assembler.h>
+
+class Op_div: public Op
+{
+public:
+ Op_div(Asm::Args& args);
+
+public:
+ std::vector<uint8_t> getCode() override
+ {
+  return machine_code;
+ }
+
+ size_t size() override
+ {
+  return machine_code.size();
+ }
+
+ bool optimize() override ///< returns true if changed
+ {
+  return false;
+ }
+
+protected:
+ std::vector<uint8_t> machine_code;
+};
+
diff --git a/asm/intel64/idiv.cpp b/asm/intel64/idiv.cpp
new file mode 100644
index 0000000..c90724f
--- /dev/null
+++ b/asm/intel64/idiv.cpp
@@ -0,0 +1,43 @@
+#include "idiv.h"
+
+#include "codes.h"
+
+#include <asm/assembler.h>
+#include <asm/operators.h>
+
+#include <asm/intel64/codes.h>
+
+using namespace std::string_literals;
+
+Op_idiv::Op_idiv(Asm::Args& args)
+{
+ if (args[0].type() == typeid(Asm::Args::Register8)) { // idiv reg8 (accu is al (remainder=ah) <- ah / reg8)
+  machine_code = std::vector<uint8_t>{ 0xF6 } +
+   ModRM("/7", std::any_cast<Asm::Args::Register8>(args[0]).name());
+ } else if (args[0].type() == typeid(Asm::Args::Register32)) { // idiv reg32 (accu is eax (remainder=edx) <- edx:eax / reg32)
+  machine_code = std::vector<uint8_t>{ 0xF7 } +
+   ModRM("/7", std::any_cast<Asm::Args::Register32>(args[0]).name());
+ } else if (args[0].type() == typeid(Asm::Args::Register64)) { // idiv reg64 (accu is rax (remainder=rdx) <- rdx:rax / reg64)
+  machine_code = REX("W") + std::vector<uint8_t>{ 0xF7 } +
+   ModRM("/7", std::any_cast<Asm::Args::Register64>(args[0]).name());
+ } else {
+  throw std::runtime_error("Unimplemented: idiv "s + args[0].type().name());
+ }
+}
+
+namespace {
+
+bool registered {
+ registerOp(mangleName<Asm::Args::Register8>("idiv"), [](Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_idiv>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Register32>("idiv"), [](Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_idiv>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Register64>("idiv"), [](Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_idiv>(args);
+            })
+};
+
+}
+
diff --git a/asm/intel64/idiv.h b/asm/intel64/idiv.h
new file mode 100644
index 0000000..a6ef411
--- /dev/null
+++ b/asm/intel64/idiv.h
@@ -0,0 +1,31 @@
+// Divide Signed Integer
+
+#pragma once
+
+#include <asm/assembler.h>
+
+class Op_idiv: public Op
+{
+public:
+ Op_idiv(Asm::Args& args);
+
+public:
+ std::vector<uint8_t> getCode() override
+ {
+  return machine_code;
+ }
+
+ size_t size() override
+ {
+  return machine_code.size();
+ }
+
+ bool optimize() override ///< returns true if changed
+ {
+  return false;
+ }
+
+protected:
+ std::vector<uint8_t> machine_code;
+};
+
diff --git a/asm/intel64/sub.cpp b/asm/intel64/sub.cpp
new file mode 100644
index 0000000..e055ee9
--- /dev/null
+++ b/asm/intel64/sub.cpp
@@ -0,0 +1,42 @@
+#include "sub.h"
+
+#include "codes.h"
+
+#include <asm/assembler.h>
+#include <asm/operators.h>
+
+using namespace std::string_literals;
+
+Op_sub::Op_sub(Asm::Args& args)
+{
+ if (args[0].type() == typeid(Asm::Args::Register32) &&
+     std::any_cast<Asm::Args::Register32>(args[0]).name() == "eax" &&
+     args[1].type() == typeid(Asm::Args::Immediate32))
+ { // sub eax, imm32 (before "sub reg32, imm32"! It's shorter.)
+  machine_code = std::vector<uint8_t>{ 0x2D } + std::any_cast<Asm::Args::Immediate32>(args[1]).getCode();
+ } else if (args[0].type() == typeid(Asm::Args::Register32) &&
+     args[1].type() == typeid(Asm::Args::Immediate32))
+ { // sub reg32, imm32
+  machine_code = std::vector<uint8_t>{ 0x81 } + ModRM("/5", std::any_cast<Asm::Args::Register32>(args[0]).name()) + std::any_cast<Asm::Args::Immediate32>(args[1]).getCode();
+ } else if (args[0].type() == typeid(Asm::Args::Register64) &&
+            std::any_cast<Asm::Args::Register64>(args[0]).name() == "rax"  &&
+            args[1].type() == typeid(Asm::Args::Immediate32))
+ { // sub reg, imm32
+  machine_code = REX("W") + machine_code = std::vector<uint8_t>{ 0x81 } + ModRM("/5", std::any_cast<Asm::Args::Register32>(args[0]).name()) + std::any_cast<Asm::Args::Immediate32>(args[1]).getCode();
+ } else {
+  throw std::runtime_error("Unimplemented: sub "s + args[0].type().name() + " "s + args[1].type().name());
+ }
+}
+
+namespace {
+
+bool registered {
+ registerOp(mangleName<Asm::Args::Register32, Asm::Args::Immediate32>("sub"), [](Asm::Args& args) -> std::shared_ptr<Op>{
+                             return std::make_shared<Op_sub>(args);
+                             }) &&
+ registerOp(mangleName<Asm::Args::Register64, Asm::Args::Immediate32>("sub"), [](Asm::Args& args) -> std::shared_ptr<Op>{
+                             return std::make_shared<Op_sub>(args);
+                             })
+};
+
+}
diff --git a/asm/intel64/sub.h b/asm/intel64/sub.h
new file mode 100644
index 0000000..cc0dd81
--- /dev/null
+++ b/asm/intel64/sub.h
@@ -0,0 +1,31 @@
+// Integer Subtraction
+
+#pragma once
+
+#include <asm/assembler.h>
+
+class Op_sub: public Op
+{
+public:
+ Op_sub(Asm::Args& args);
+
+public:
+ std::vector<uint8_t> getCode() override
+ {
+  return machine_code;
+ }
+
+ size_t size() override
+ {
+  return machine_code.size();
+ }
+
+ bool optimize() override ///< returns true if changed
+ {
+  return false;
+ }
+
+protected:
+ std::vector<uint8_t> machine_code;
+};
+