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-rw-r--r--Makefile1
-rw-r--r--README4
-rw-r--r--asm/intel64/all_ops.h1
-rw-r--r--asm/intel64/cmp.cpp114
-rw-r--r--asm/intel64/cmp.h31
-rw-r--r--asm/intel64/encode.cpp1
6 files changed, 150 insertions, 2 deletions
diff --git a/Makefile b/Makefile
index dd8347d..eb1bd62 100644
--- a/Makefile
+++ b/Makefile
@@ -52,6 +52,7 @@ PROGSRC=\
asm/intel64/and.cpp \
asm/intel64/bsf.cpp \
asm/intel64/bsr.cpp \
+ asm/intel64/cmp.cpp \
asm/intel64/dec.cpp \
asm/intel64/div.cpp \
asm/intel64/idiv.cpp \
diff --git a/README b/README
index 5083618..4009a62 100644
--- a/README
+++ b/README
@@ -1,5 +1,5 @@
-MCC - Mini Compiler Collection
-==============================
+MiniCC - Minimal Incomplete Intel Compiler Collection
+=====================================================
Build
-----
diff --git a/asm/intel64/all_ops.h b/asm/intel64/all_ops.h
index 89313b2..f9dc05b 100644
--- a/asm/intel64/all_ops.h
+++ b/asm/intel64/all_ops.h
@@ -4,6 +4,7 @@
#include "and.h"
#include "bsf.h"
#include "bsr.h"
+#include "cmp.h"
#include "dec.h"
#include "div.h"
#include "idiv.h"
diff --git a/asm/intel64/cmp.cpp b/asm/intel64/cmp.cpp
new file mode 100644
index 0000000..3a2a582
--- /dev/null
+++ b/asm/intel64/cmp.cpp
@@ -0,0 +1,114 @@
+#include "cmp.h"
+
+#include "codes.h"
+
+#include <asm/assembler.h>
+#include <asm/operators.h>
+
+using namespace std::string_literals;
+
+Op_cmp::Op_cmp(const Asm::Args& args)
+{
+ if (args[0].type() == typeid(Asm::Args::Register32) &&
+ std::any_cast<Asm::Args::Register32>(args[0]).name() == "eax" &&
+ args[1].type() == typeid(Asm::Args::Immediate32))
+ { // cmp eax, imm32 (before "cmp reg32, imm32"! It's shorter.)
+ machine_code = std::vector<uint8_t>{ 0x3D } + std::any_cast<Asm::Args::Immediate32>(args[1]).getCode();
+
+ } else if (args[0].type() == typeid(Asm::Args::Register32) &&
+ args[1].type() == typeid(Asm::Args::Immediate32))
+ { // cmp reg32, imm32
+ machine_code = std::vector<uint8_t>{ 0x81 } + ModRM("/7", std::any_cast<Asm::Args::Register32>(args[0]).name()) + std::any_cast<Asm::Args::Immediate32>(args[1]).getCode();
+
+ } else if (args[0].type() == typeid(Asm::Args::Register64) &&
+ std::any_cast<Asm::Args::Register64>(args[0]).name() == "rax" &&
+ args[1].type() == typeid(Asm::Args::Immediate32))
+
+ { // cmp rax, imm32 (sign extended)
+ machine_code = REX("W") + std::vector<uint8_t>{ 0x3D } + std::any_cast<Asm::Args::Immediate32>(args[1]).getCode();
+
+ } else if (args[0].type() == typeid(Asm::Args::Register8) && args[1].type() == typeid(Asm::Args::Register8)) { // cmp reg8, reg8
+ machine_code = std::vector<uint8_t>{ 0x38 } + ModRM(std::any_cast<Asm::Args::Register8>(args[1]).name(), std::any_cast<Asm::Args::Register8>(args[0]).name());
+
+ } else if (args[0].type() == typeid(Asm::Args::Register16) && args[1].type() == typeid(Asm::Args::Register16)) { // cmp reg16, reg16
+ machine_code = OpSizePrefix() + std::vector<uint8_t>{ 0x39 } + ModRM(std::any_cast<Asm::Args::Register8>(args[1]).name(), std::any_cast<Asm::Args::Register8>(args[0]).name());
+
+ } else if (args[0].type() == typeid(Asm::Args::Register32) && args[1].type() == typeid(Asm::Args::Register32)) { // cmp reg32, reg32
+ machine_code = std::vector<uint8_t>{ 0x39 } + ModRM(std::any_cast<Asm::Args::Register32>(args[1]).name(), std::any_cast<Asm::Args::Register32>(args[0]).name());
+
+ } else if (args[0].type() == typeid(Asm::Args::Register64) && args[1].type() == typeid(Asm::Args::Register64)) { // cmp reg64, reg64
+ machine_code = REX("W") + std::vector<uint8_t>{ 0x39 } + ModRM(std::any_cast<Asm::Args::Register64>(args[1]).name(), std::any_cast<Asm::Args::Register64>(args[0]).name());
+
+ } else if (args[0].type() == typeid(Asm::Args::Register32) && args[1].type() == typeid(Asm::Args::Mem32Ptr64)) { // cmp reg32, [reg64]
+ Asm::Args::Mem32Ptr64 ptr{std::any_cast<Asm::Args::Mem32Ptr64>(args[1])};
+ machine_code = std::vector<uint8_t>{ 0x3B } + ModRM(std::any_cast<Asm::Args::Register32>(args[0]).name(), ptr.reg(), ptr.offs());
+
+ } else if (args[0].type() == typeid(Asm::Args::Register64) && args[1].type() == typeid(Asm::Args::Mem64Ptr64)) { // cmp reg64, [reg64]
+ Asm::Args::Mem64Ptr64 ptr{std::any_cast<Asm::Args::Mem64Ptr64>(args[1])};
+ machine_code = REX("W") + std::vector<uint8_t>{ 0x3B } + ModRM(std::any_cast<Asm::Args::Register64>(args[0]).name(), ptr.reg(), ptr.offs());
+
+ } else if (args[0].type() == typeid(Asm::Args::Mem8Ptr64) && args[1].type() == typeid(Asm::Args::Immediate8)) { // cmp [reg64], imm8
+ Asm::Args::Mem8Ptr64 ptr{std::any_cast<Asm::Args::Mem8Ptr64>(args[0])};
+ machine_code = std::vector<uint8_t>{ 0x80 } + ModRM("/7", ptr.reg(), ptr.offs()) + std::any_cast<Asm::Args::Immediate8>(args[1]).getCode();
+
+ } else if (args[0].type() == typeid(Asm::Args::Mem32Ptr64) && args[1].type() == typeid(Asm::Args::Immediate32)) { // cmp [reg64], imm32
+ Asm::Args::Mem32Ptr64 ptr{std::any_cast<Asm::Args::Mem32Ptr64>(args[0])};
+ machine_code = std::vector<uint8_t>{ 0x81 } + ModRM("/7", ptr.reg(), ptr.offs()) + std::any_cast<Asm::Args::Immediate32>(args[1]).getCode();
+
+ } else if (args[0].type() == typeid(Asm::Args::Mem64Ptr64) && args[1].type() == typeid(Asm::Args::Immediate32)) { // cmp qword ptr [reg64], imm32 (sign-extended)
+ Asm::Args::Mem64Ptr64 ptr{std::any_cast<Asm::Args::Mem64Ptr64>(args[0])};
+ machine_code = REX("W") + std::vector<uint8_t>{ 0x81 } + ModRM("/7", ptr.reg(), ptr.offs()) + std::any_cast<Asm::Args::Immediate32>(args[1]).getCode();
+
+ } else if (args[0].type() == typeid(Asm::Args::Mem64Ptr64) && args[1].type() == typeid(Asm::Args::Immediate64)) { // cmp qword ptr [reg64], imm32 (sign-extended) - reduce imm64 to imm32!
+ Asm::Args::Mem64Ptr64 ptr{std::any_cast<Asm::Args::Mem64Ptr64>(args[0])};
+ Asm::Args::Immediate32 imm32{std::any_cast<Asm::Args::Immediate64>(args[1])};
+ machine_code = REX("W") + std::vector<uint8_t>{ 0x81 } + ModRM("/7", ptr.reg(), ptr.offs()) + imm32.getCode();
+
+ } else {
+ throw std::runtime_error("Unimplemented: cmp "s + args[0].type().name() + " "s + args[1].type().name());
+ }
+}
+
+namespace {
+
+bool registered {
+ registerOp(mangleName<Asm::Args::Register32, Asm::Args::Immediate32>("cmp"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+ return std::make_shared<Op_cmp>(args);
+ }) &&
+ registerOp(mangleName<Asm::Args::Register64, Asm::Args::Immediate32>("cmp"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+ return std::make_shared<Op_cmp>(args);
+ }) &&
+ registerOp(mangleName<Asm::Args::Register8, Asm::Args::Register8>("cmp"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+ return std::make_shared<Op_cmp>(args);
+ }) &&
+ registerOp(mangleName<Asm::Args::Register16, Asm::Args::Register16>("cmp"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+ return std::make_shared<Op_cmp>(args);
+ }) &&
+ registerOp(mangleName<Asm::Args::Register32, Asm::Args::Register32>("cmp"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+ return std::make_shared<Op_cmp>(args);
+ }) &&
+ registerOp(mangleName<Asm::Args::Register64, Asm::Args::Register64>("cmp"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+ return std::make_shared<Op_cmp>(args);
+ }) &&
+ registerOp(mangleName<Asm::Args::Register32, Asm::Args::Mem32Ptr64>("cmp"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+ return std::make_shared<Op_cmp>(args);
+ }) &&
+ registerOp(mangleName<Asm::Args::Register64, Asm::Args::Mem64Ptr64>("cmp"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+ return std::make_shared<Op_cmp>(args);
+ }) &&
+ registerOp(mangleName<Asm::Args::Mem8Ptr64, Asm::Args::Immediate8>("cmp"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+ return std::make_shared<Op_cmp>(args);
+ }) &&
+ registerOp(mangleName<Asm::Args::Mem32Ptr64, Asm::Args::Immediate32>("cmp"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+ return std::make_shared<Op_cmp>(args);
+ }) &&
+ registerOp(mangleName<Asm::Args::Mem64Ptr64, Asm::Args::Immediate32>("cmp"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+ return std::make_shared<Op_cmp>(args);
+ }) &&
+ registerOp(mangleName<Asm::Args::Mem64Ptr64, Asm::Args::Immediate64>("cmp"), [](const Asm::Args& args) -> std::shared_ptr<Op>{ // automatically converted to 32-bit (sign extended) if small enough. Intel doesn't support CMP ..., imm64
+ return std::make_shared<Op_cmp>(args);
+ })
+};
+
+}
+
diff --git a/asm/intel64/cmp.h b/asm/intel64/cmp.h
new file mode 100644
index 0000000..7cad008
--- /dev/null
+++ b/asm/intel64/cmp.h
@@ -0,0 +1,31 @@
+// Compare Two Operands
+
+#pragma once
+
+#include <asm/assembler.h>
+
+class Op_cmp: public Op
+{
+public:
+ Op_cmp(const Asm::Args& args);
+
+public:
+ std::vector<uint8_t> getCode() override
+ {
+ return machine_code;
+ }
+
+ size_t size() override
+ {
+ return machine_code.size();
+ }
+
+ bool optimize() override ///< returns true if changed
+ {
+ return false;
+ }
+
+protected:
+ std::vector<uint8_t> machine_code;
+};
+
diff --git a/asm/intel64/encode.cpp b/asm/intel64/encode.cpp
index 0d7eacb..388639d 100644
--- a/asm/intel64/encode.cpp
+++ b/asm/intel64/encode.cpp
@@ -225,6 +225,7 @@ void Asm::toMachineCode(const FlowGraph::Graph& graph, Segment& segment)
segment.push_back(makeStoreValue(operands[0], graph));
} else if (op.type() == FlowGraph::UnaryOperationType::LogicalNot) {
segment.push_back(makeLoadValue(operands[1], graph));
+ // TODO: cmp eax, 0 \n sete al \n movsx eax, al
segment.append(parseAsm("bsr eax")); // ZF=1 iff eax=0
segment.append(parseAsm("lahf")); // ZF in AH bit 6
segment.append(parseAsm("shr eax, 14")); // ZF in eax bit 0
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