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-rw-r--r--asm/intel64/encode.cpp34
-rw-r--r--asm/intel64/rcl.cpp8
-rw-r--r--asm/intel64/rcr.cpp8
-rw-r--r--asm/intel64/rol.cpp8
-rw-r--r--asm/intel64/ror.cpp8
-rw-r--r--asm/intel64/sal_shl.cpp8
-rw-r--r--asm/intel64/sar.cpp8
-rw-r--r--asm/intel64/shr.cpp8
-rw-r--r--cpp.cpp5
-rw-r--r--systemtest/mcc-execute.tests/exitcodes.exp1
-rw-r--r--systemtest/mcc-execute.tests/test-shift-left.cpp1
11 files changed, 69 insertions, 28 deletions
diff --git a/asm/intel64/encode.cpp b/asm/intel64/encode.cpp
index d3bfd91..6c18d1c 100644
--- a/asm/intel64/encode.cpp
+++ b/asm/intel64/encode.cpp
@@ -6,6 +6,7 @@
#include "byteorder.h"
#include "minicc.h"
+#include <algorithm>
#include <exception>
namespace {
@@ -170,6 +171,35 @@ std::vector<std::shared_ptr<Chunk>> makeDivValue(const FlowGraph::Data& data, co
throw std::runtime_error("ICE: Unsupported type for operand data at div: "s + demangle(typeid(data_storage)));
}
+std::shared_ptr<Op> makeShiftLeftValue(const FlowGraph::Data& data, const FlowGraph::Graph& graph)
+{
+ if (data.type() != FlowGraph::DataType::Int) {
+ throw std::runtime_error("Bad type for operand: "s + std::to_string(int(data.type())));
+ }
+
+ if (!data.storage())
+ throw std::runtime_error("ICE: Operand storage is 0");
+
+ auto& data_storage{*data.storage()};
+ if (typeid(data_storage) == typeid(FlowGraph::Constant)) {
+ FlowGraph::Constant& value {dynamic_cast<FlowGraph::Constant&>(data_storage)};
+ if (value.value().size() < sizeof(uint32_t))
+ throw std::runtime_error("ICE: Int data from operand needs at least 4 bytes, got "s + std::to_string(value.value().size()));
+
+ uint32_t immediate = endian::from_little32(value.value());
+ immediate = std::min(immediate, uint32_t(0xFF));
+
+ return makeOp("shl", Asm::Args{{Asm::Args::Register32("eax"), Asm::Args::Immediate8(static_cast<uint8_t>(immediate))}});
+ } else if (typeid(data_storage) == typeid(FlowGraph::TemporaryStorage)) {
+ //FlowGraph::TemporaryStorage& storage {dynamic_cast<FlowGraph::TemporaryStorage&>(data_storage)};
+
+ index_t index { graph.scope()->indexOfData(data)};
+ // makeOp("mov", Asm::Args{{Asm::Args::Register32("ecx"), Asm::Args::Mem32Ptr64("rbp", int32_t(index + 1) * -4)}}); // TODO: return list of ops; limit ecx to 0xff; implement shr x, cl
+ return makeOp("nop");//makeOp("shl", Asm::Args{{Asm::Args::Register32("eax"), Asm::Args::Register8("cl")}});
+ } else
+ throw std::runtime_error("ICE: Unsupported type for operand data at shift left: "s + demangle(typeid(data_storage)));
+}
+
} // namespace
void Asm::toMachineCode(const FlowGraph::Graph& graph, Segment& segment)
@@ -238,6 +268,10 @@ void Asm::toMachineCode(const FlowGraph::Graph& graph, Segment& segment)
segment.append(makeDivValue(operands[2], graph));
segment.append(parseAsm("mov eax, edx")); // remainder is in edx
segment.push_back(makeStoreValue(operands[0], graph));
+ } else if (op.type() == FlowGraph::BinaryOperationType::ShiftLeft) {
+ segment.push_back(makeLoadValue(operands[1], graph));
+ segment.push_back(makeShiftLeftValue(operands[2], graph));
+ segment.push_back(makeStoreValue(operands[0], graph));
} else
throw std::runtime_error("ICE: Asm: Unsupported binary operation type: "s + std::to_string(static_cast<int>(op.type())));
diff --git a/asm/intel64/rcl.cpp b/asm/intel64/rcl.cpp
index 038f3d3..35f37db 100644
--- a/asm/intel64/rcl.cpp
+++ b/asm/intel64/rcl.cpp
@@ -15,17 +15,17 @@ Op_rcl::Op_rcl(const Asm::Args& args)
if (args[0].type() == typeid(Asm::Args::Register8)) { // rcl reg8, 1
machine_code = std::vector<uint8_t>{ 0xD0 } + ModRM("/2", std::any_cast<Asm::Args::Register8>(args[0]).name());
} else if (args[0].type() == typeid(Asm::Args::Register32)) { // rcl reg32, 1
- machine_code = std::vector<uint8_t>{ 0xD1 } + ModRM("/2", std::any_cast<Asm::Args::Register8>(args[0]).name());
+ machine_code = std::vector<uint8_t>{ 0xD1 } + ModRM("/2", std::any_cast<Asm::Args::Register32>(args[0]).name());
} else if (args[0].type() == typeid(Asm::Args::Register64)) { // rcl reg64, 1
- machine_code = REX("W") + std::vector<uint8_t>{ 0xD1 } + ModRM("/2", std::any_cast<Asm::Args::Register8>(args[0]).name());
+ machine_code = REX("W") + std::vector<uint8_t>{ 0xD1 } + ModRM("/2", std::any_cast<Asm::Args::Register64>(args[0]).name());
}
} else { // general version >= 2 bits shift
if (args[0].type() == typeid(Asm::Args::Register8)) { // rcl reg8, imm8
machine_code = std::vector<uint8_t>{ 0xC0 } + ModRM("/2", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset;
} else if (args[0].type() == typeid(Asm::Args::Register32)) { // rcl reg32, imm8
- machine_code = std::vector<uint8_t>{ 0xC1 } + ModRM("/2", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset;
+ machine_code = std::vector<uint8_t>{ 0xC1 } + ModRM("/2", std::any_cast<Asm::Args::Register32>(args[0]).name()) + shift_offset;
} else if (args[0].type() == typeid(Asm::Args::Register64)) { // rcl reg64, imm8
- machine_code = REX("W") + std::vector<uint8_t>{ 0xC1 } + ModRM("/2", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset;
+ machine_code = REX("W") + std::vector<uint8_t>{ 0xC1 } + ModRM("/2", std::any_cast<Asm::Args::Register64>(args[0]).name()) + shift_offset;
}
}
diff --git a/asm/intel64/rcr.cpp b/asm/intel64/rcr.cpp
index 27b688c..c2bc532 100644
--- a/asm/intel64/rcr.cpp
+++ b/asm/intel64/rcr.cpp
@@ -15,17 +15,17 @@ Op_rcr::Op_rcr(const Asm::Args& args)
if (args[0].type() == typeid(Asm::Args::Register8)) { // rcr reg8, 1
machine_code = std::vector<uint8_t>{ 0xD0 } + ModRM("/3", std::any_cast<Asm::Args::Register8>(args[0]).name());
} else if (args[0].type() == typeid(Asm::Args::Register32)) { // rcr reg32, 1
- machine_code = std::vector<uint8_t>{ 0xD1 } + ModRM("/3", std::any_cast<Asm::Args::Register8>(args[0]).name());
+ machine_code = std::vector<uint8_t>{ 0xD1 } + ModRM("/3", std::any_cast<Asm::Args::Register32>(args[0]).name());
} else if (args[0].type() == typeid(Asm::Args::Register64)) { // rcr reg64, 1
- machine_code = REX("W") + std::vector<uint8_t>{ 0xD1 } + ModRM("/3", std::any_cast<Asm::Args::Register8>(args[0]).name());
+ machine_code = REX("W") + std::vector<uint8_t>{ 0xD1 } + ModRM("/3", std::any_cast<Asm::Args::Register64>(args[0]).name());
}
} else { // general version >= 2 bits shift
if (args[0].type() == typeid(Asm::Args::Register8)) { // rcr reg8, imm8
machine_code = std::vector<uint8_t>{ 0xC0 } + ModRM("/3", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset;
} else if (args[0].type() == typeid(Asm::Args::Register32)) { // rcr reg32, imm8
- machine_code = std::vector<uint8_t>{ 0xC1 } + ModRM("/3", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset;
+ machine_code = std::vector<uint8_t>{ 0xC1 } + ModRM("/3", std::any_cast<Asm::Args::Register32>(args[0]).name()) + shift_offset;
} else if (args[0].type() == typeid(Asm::Args::Register64)) { // rcr reg64, imm8
- machine_code = REX("W") + std::vector<uint8_t>{ 0xC1 } + ModRM("/3", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset;
+ machine_code = REX("W") + std::vector<uint8_t>{ 0xC1 } + ModRM("/3", std::any_cast<Asm::Args::Register64>(args[0]).name()) + shift_offset;
}
}
diff --git a/asm/intel64/rol.cpp b/asm/intel64/rol.cpp
index 98d69d9..98e3909 100644
--- a/asm/intel64/rol.cpp
+++ b/asm/intel64/rol.cpp
@@ -15,17 +15,17 @@ Op_rol::Op_rol(const Asm::Args& args)
if (args[0].type() == typeid(Asm::Args::Register8)) { // rol reg8, 1
machine_code = std::vector<uint8_t>{ 0xD0 } + ModRM("/0", std::any_cast<Asm::Args::Register8>(args[0]).name());
} else if (args[0].type() == typeid(Asm::Args::Register32)) { // rol reg32, 1
- machine_code = std::vector<uint8_t>{ 0xD1 } + ModRM("/0", std::any_cast<Asm::Args::Register8>(args[0]).name());
+ machine_code = std::vector<uint8_t>{ 0xD1 } + ModRM("/0", std::any_cast<Asm::Args::Register32>(args[0]).name());
} else if (args[0].type() == typeid(Asm::Args::Register64)) { // rol reg64, 1
- machine_code = REX("W") + std::vector<uint8_t>{ 0xD1 } + ModRM("/0", std::any_cast<Asm::Args::Register8>(args[0]).name());
+ machine_code = REX("W") + std::vector<uint8_t>{ 0xD1 } + ModRM("/0", std::any_cast<Asm::Args::Register64>(args[0]).name());
}
} else { // general version >= 2 bits shift
if (args[0].type() == typeid(Asm::Args::Register8)) { // rol reg8, imm8
machine_code = std::vector<uint8_t>{ 0xC0 } + ModRM("/0", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset;
} else if (args[0].type() == typeid(Asm::Args::Register32)) { // rol reg32, imm8
- machine_code = std::vector<uint8_t>{ 0xC1 } + ModRM("/0", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset;
+ machine_code = std::vector<uint8_t>{ 0xC1 } + ModRM("/0", std::any_cast<Asm::Args::Register32>(args[0]).name()) + shift_offset;
} else if (args[0].type() == typeid(Asm::Args::Register64)) { // rol reg64, imm8
- machine_code = REX("W") + std::vector<uint8_t>{ 0xC1 } + ModRM("/0", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset;
+ machine_code = REX("W") + std::vector<uint8_t>{ 0xC1 } + ModRM("/0", std::any_cast<Asm::Args::Register64>(args[0]).name()) + shift_offset;
}
}
diff --git a/asm/intel64/ror.cpp b/asm/intel64/ror.cpp
index 70a7a6b..13f536d 100644
--- a/asm/intel64/ror.cpp
+++ b/asm/intel64/ror.cpp
@@ -15,17 +15,17 @@ Op_ror::Op_ror(const Asm::Args& args)
if (args[0].type() == typeid(Asm::Args::Register8)) { // ror reg8, 1
machine_code = std::vector<uint8_t>{ 0xD0 } + ModRM("/1", std::any_cast<Asm::Args::Register8>(args[0]).name());
} else if (args[0].type() == typeid(Asm::Args::Register32)) { // ror reg32, 1
- machine_code = std::vector<uint8_t>{ 0xD1 } + ModRM("/1", std::any_cast<Asm::Args::Register8>(args[0]).name());
+ machine_code = std::vector<uint8_t>{ 0xD1 } + ModRM("/1", std::any_cast<Asm::Args::Register32>(args[0]).name());
} else if (args[0].type() == typeid(Asm::Args::Register64)) { // ror reg64, 1
- machine_code = REX("W") + std::vector<uint8_t>{ 0xD1 } + ModRM("/1", std::any_cast<Asm::Args::Register8>(args[0]).name());
+ machine_code = REX("W") + std::vector<uint8_t>{ 0xD1 } + ModRM("/1", std::any_cast<Asm::Args::Register64>(args[0]).name());
}
} else { // general version >= 2 bits shift
if (args[0].type() == typeid(Asm::Args::Register8)) { // ror reg8, imm8
machine_code = std::vector<uint8_t>{ 0xC0 } + ModRM("/1", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset;
} else if (args[0].type() == typeid(Asm::Args::Register32)) { // ror reg32, imm8
- machine_code = std::vector<uint8_t>{ 0xC1 } + ModRM("/1", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset;
+ machine_code = std::vector<uint8_t>{ 0xC1 } + ModRM("/1", std::any_cast<Asm::Args::Register32>(args[0]).name()) + shift_offset;
} else if (args[0].type() == typeid(Asm::Args::Register64)) { // ror reg64, imm8
- machine_code = REX("W") + std::vector<uint8_t>{ 0xC1 } + ModRM("/1", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset;
+ machine_code = REX("W") + std::vector<uint8_t>{ 0xC1 } + ModRM("/1", std::any_cast<Asm::Args::Register64>(args[0]).name()) + shift_offset;
}
}
diff --git a/asm/intel64/sal_shl.cpp b/asm/intel64/sal_shl.cpp
index c822666..8dbfb24 100644
--- a/asm/intel64/sal_shl.cpp
+++ b/asm/intel64/sal_shl.cpp
@@ -15,17 +15,17 @@ Op_sal::Op_sal(const Asm::Args& args)
if (args[0].type() == typeid(Asm::Args::Register8)) { // sal reg8, 1
machine_code = std::vector<uint8_t>{ 0xD0 } + ModRM("/4", std::any_cast<Asm::Args::Register8>(args[0]).name());
} else if (args[0].type() == typeid(Asm::Args::Register32)) { // sal reg32, 1
- machine_code = std::vector<uint8_t>{ 0xD1 } + ModRM("/4", std::any_cast<Asm::Args::Register8>(args[0]).name());
+ machine_code = std::vector<uint8_t>{ 0xD1 } + ModRM("/4", std::any_cast<Asm::Args::Register32>(args[0]).name());
} else if (args[0].type() == typeid(Asm::Args::Register64)) { // sal reg64, 1
- machine_code = REX("W") + std::vector<uint8_t>{ 0xD1 } + ModRM("/4", std::any_cast<Asm::Args::Register8>(args[0]).name());
+ machine_code = REX("W") + std::vector<uint8_t>{ 0xD1 } + ModRM("/4", std::any_cast<Asm::Args::Register64>(args[0]).name());
}
} else { // general version >= 2 bits shift
if (args[0].type() == typeid(Asm::Args::Register8)) { // sal reg8, imm8
machine_code = std::vector<uint8_t>{ 0xC0 } + ModRM("/4", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset;
} else if (args[0].type() == typeid(Asm::Args::Register32)) { // sal reg32, imm8
- machine_code = std::vector<uint8_t>{ 0xC1 } + ModRM("/4", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset;
+ machine_code = std::vector<uint8_t>{ 0xC1 } + ModRM("/4", std::any_cast<Asm::Args::Register32>(args[0]).name()) + shift_offset;
} else if (args[0].type() == typeid(Asm::Args::Register64)) { // sal reg64, imm8
- machine_code = REX("W") + std::vector<uint8_t>{ 0xC1 } + ModRM("/4", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset;
+ machine_code = REX("W") + std::vector<uint8_t>{ 0xC1 } + ModRM("/4", std::any_cast<Asm::Args::Register64>(args[0]).name()) + shift_offset;
}
}
diff --git a/asm/intel64/sar.cpp b/asm/intel64/sar.cpp
index fccd738..3ca8a86 100644
--- a/asm/intel64/sar.cpp
+++ b/asm/intel64/sar.cpp
@@ -15,17 +15,17 @@ Op_sar::Op_sar(const Asm::Args& args)
if (args[0].type() == typeid(Asm::Args::Register8)) { // sar reg8, 1
machine_code = std::vector<uint8_t>{ 0xD0 } + ModRM("/7", std::any_cast<Asm::Args::Register8>(args[0]).name());
} else if (args[0].type() == typeid(Asm::Args::Register32)) { // sar reg32, 1
- machine_code = std::vector<uint8_t>{ 0xD1 } + ModRM("/7", std::any_cast<Asm::Args::Register8>(args[0]).name());
+ machine_code = std::vector<uint8_t>{ 0xD1 } + ModRM("/7", std::any_cast<Asm::Args::Register32>(args[0]).name());
} else if (args[0].type() == typeid(Asm::Args::Register64)) { // sar reg64, 1
- machine_code = REX("W") + std::vector<uint8_t>{ 0xD1 } + ModRM("/7", std::any_cast<Asm::Args::Register8>(args[0]).name());
+ machine_code = REX("W") + std::vector<uint8_t>{ 0xD1 } + ModRM("/7", std::any_cast<Asm::Args::Register64>(args[0]).name());
}
} else { // general version >= 2 bits shift
if (args[0].type() == typeid(Asm::Args::Register8)) { // sar reg8, imm8
machine_code = std::vector<uint8_t>{ 0xC0 } + ModRM("/7", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset;
} else if (args[0].type() == typeid(Asm::Args::Register32)) { // sar reg32, imm8
- machine_code = std::vector<uint8_t>{ 0xC1 } + ModRM("/7", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset;
+ machine_code = std::vector<uint8_t>{ 0xC1 } + ModRM("/7", std::any_cast<Asm::Args::Register32>(args[0]).name()) + shift_offset;
} else if (args[0].type() == typeid(Asm::Args::Register64)) { // sar reg64, imm8
- machine_code = REX("W") + std::vector<uint8_t>{ 0xC1 } + ModRM("/7", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset;
+ machine_code = REX("W") + std::vector<uint8_t>{ 0xC1 } + ModRM("/7", std::any_cast<Asm::Args::Register64>(args[0]).name()) + shift_offset;
}
}
diff --git a/asm/intel64/shr.cpp b/asm/intel64/shr.cpp
index 01977b0..b85fc71 100644
--- a/asm/intel64/shr.cpp
+++ b/asm/intel64/shr.cpp
@@ -15,17 +15,17 @@ Op_shr::Op_shr(const Asm::Args& args)
if (args[0].type() == typeid(Asm::Args::Register8)) { // shr reg8, 1
machine_code = std::vector<uint8_t>{ 0xD0 } + ModRM("/5", std::any_cast<Asm::Args::Register8>(args[0]).name());
} else if (args[0].type() == typeid(Asm::Args::Register32)) { // shr reg32, 1
- machine_code = std::vector<uint8_t>{ 0xD1 } + ModRM("/5", std::any_cast<Asm::Args::Register8>(args[0]).name());
+ machine_code = std::vector<uint8_t>{ 0xD1 } + ModRM("/5", std::any_cast<Asm::Args::Register32>(args[0]).name());
} else if (args[0].type() == typeid(Asm::Args::Register64)) { // shr reg64, 1
- machine_code = REX("W") + std::vector<uint8_t>{ 0xD1 } + ModRM("/5", std::any_cast<Asm::Args::Register8>(args[0]).name());
+ machine_code = REX("W") + std::vector<uint8_t>{ 0xD1 } + ModRM("/5", std::any_cast<Asm::Args::Register64>(args[0]).name());
}
} else { // general version >= 2 bits shift
if (args[0].type() == typeid(Asm::Args::Register8)) { // shr reg8, imm8
machine_code = std::vector<uint8_t>{ 0xC0 } + ModRM("/5", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset;
} else if (args[0].type() == typeid(Asm::Args::Register32)) { // shr reg32, imm8
- machine_code = std::vector<uint8_t>{ 0xC1 } + ModRM("/5", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset;
+ machine_code = std::vector<uint8_t>{ 0xC1 } + ModRM("/5", std::any_cast<Asm::Args::Register32>(args[0]).name()) + shift_offset;
} else if (args[0].type() == typeid(Asm::Args::Register64)) { // shr reg64, imm8
- machine_code = REX("W") + std::vector<uint8_t>{ 0xC1 } + ModRM("/5", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset;
+ machine_code = REX("W") + std::vector<uint8_t>{ 0xC1 } + ModRM("/5", std::any_cast<Asm::Args::Register64>(args[0]).name()) + shift_offset;
}
}
diff --git a/cpp.cpp b/cpp.cpp
index cefd5fd..15dfc87 100644
--- a/cpp.cpp
+++ b/cpp.cpp
@@ -390,6 +390,8 @@ std::unordered_map<std::string, FlowGraph::BinaryOperationType> binaryOperations
{"*", FlowGraph::BinaryOperationType::Multiply},
{"/", FlowGraph::BinaryOperationType::Divide},
{"%", FlowGraph::BinaryOperationType::Modulo},
+ {"<<", FlowGraph::BinaryOperationType::ShiftLeft},
+ {">>", FlowGraph::BinaryOperationType::ShiftRight},
};
} // namespace
@@ -492,6 +494,9 @@ std::unordered_map<std::string, std::function<std::any(index_t)>> CPP::getNodeEv
},
{ "shift-expression", [&](index_t index) -> std::any
{
+ if (childTypesOfNodeMatch(index, {"shift-expression", "", "additive-expression"})) {
+ return BinaryOperation(index);
+ }
if (childTypesOfNodeMatch(index, {"additive-expression"}))
return getValue(index, 0);
throw std::runtime_error("ICE: Unsupported childs: "s + ruleString(index)); // TODO
diff --git a/systemtest/mcc-execute.tests/exitcodes.exp b/systemtest/mcc-execute.tests/exitcodes.exp
index fcd70ec..1f84444 100644
--- a/systemtest/mcc-execute.tests/exitcodes.exp
+++ b/systemtest/mcc-execute.tests/exitcodes.exp
@@ -9,4 +9,5 @@ runtest_exit_code "Modulo" "systemtest/mcc-execute.tests/test-modulo" 1
runtest_exit_code "Parentheses Tree" "systemtest/mcc-execute.tests/test-parentheses" 36
runtest_exit_code "Parentheses Left" "systemtest/mcc-execute.tests/test-parentheses-left" 36
runtest_exit_code "Parentheses Right" "systemtest/mcc-execute.tests/test-parentheses-right" 36
+runtest_exit_code "Shift Left" "systemtest/mcc-execute.tests/test-shift-left" 12
diff --git a/systemtest/mcc-execute.tests/test-shift-left.cpp b/systemtest/mcc-execute.tests/test-shift-left.cpp
new file mode 100644
index 0000000..410ab2b
--- /dev/null
+++ b/systemtest/mcc-execute.tests/test-shift-left.cpp
@@ -0,0 +1 @@
+int main() { return 3 << 2; }
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