diff options
| -rw-r--r-- | asm/arm/instruction.h | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/asm/arm/instruction.h b/asm/arm/instruction.h index 54cc8ca..d8d4033 100644 --- a/asm/arm/instruction.h +++ b/asm/arm/instruction.h @@ -1,6 +1,7 @@ #pragma once #include <memory> +#include <optional> #include <stdexcept> #include <string> #include <vector> @@ -107,9 +108,11 @@ namespace { std::shared_ptr<Operand> imm(uint8_t size, uint8_t pos, uint8_t factor = 1, uint32_t code0_is_value = 0, const std::vector<uint32_t>& invalid_values = {}){ return std::make_shared<Immediate>(size, pos); } std::shared_ptr<Operand> label(uint8_t size, uint8_t pos, uint8_t factor = 1, bool is_signed = false){ return std::make_shared<Immediate>(size, pos); } std::shared_ptr<Operand> label(uint8_t size, const std::vector<uint8_t>& bits, uint32_t flip_mask, uint8_t factor = 1, bool is_signed = false){ throw std::runtime_error("Unimplemented: label w/ flipmask"); } - std::shared_ptr<Operand> reg(uint8_t size, uint8_t pos) { return std::make_shared<Register>(size, pos); } + // reg_list_ref_index, see LDM + std::shared_ptr<Operand> reg(uint8_t size, uint8_t pos, std::optional<uint8_t> reg_list_ref_index = std::nullopt) { return std::make_shared<Register>(size, pos); } std::shared_ptr<Operand> reg(uint32_t mask) { return std::make_shared<Register>(mask); } std::shared_ptr<Operand> reg(const std::string& name) { return std::make_shared<Register>(name); } + std::shared_ptr<Operand> reg_list(uint8_t size, uint8_t pos) { throw std::runtime_error("Unimplemented: reg_list"); } std::shared_ptr<Operand> id(const std::string& name) { throw std::runtime_error("Unimplemented: id"); } std::shared_ptr<Operand> same_reg(uint8_t index) { return std::make_shared<SameRegister>(index); } std::shared_ptr<Operand> cond(uint8_t pos) { throw std::runtime_error("Unimplemented: cond"); } @@ -149,8 +152,14 @@ namespace { {"cmp", 2, Pattern(0x4500, high_bits(8)), Operands{reg(0x87), reg(4, 3)}}, // T2 {"cps", 2, Pattern(0xB662, 0xFFEF), Operands{imm(1, 4)}}, // T1 {"cpy", 2, Pattern(0x4600, high_bits(8), true), Operands{reg(0x87), reg(4, 3)}}, // T1 - {"dmb", 4, Pattern(0xF3BF8F5F, high_bits(32)), Operands{id("sy")}}, // T1 - {"dsb", 4, Pattern(0xF3BF8F4F, high_bits(32)), Operands{id("sy")}}, // T1 + {"dmb", 4, Pattern(0xF3BF8F5F, high_bits(32)), Operands{optional(id("sy"))}}, // T1 + {"dsb", 4, Pattern(0xF3BF8F4F, high_bits(32)), Operands{optional(id("sy"))}}, // T1 + {"eors", 2, Pattern(0x4040, high_bits(10)), Operands{optional(same_reg(1)), reg(3, 0), reg(3, 3)}}, // T1 + {"isb", 4, Pattern(0xF3BF8F6F, high_bits(32)), Operands{optional(id("sy"))}}, // T1 + {"ldm", 2, Pattern(0xC800, high_bits(5)), Operands{reg(3, 8, 1), reg_list(8, 0)}}, // T1 + {"ldm", 2, Pattern(0xC800, high_bits(5)), Operands{reg(3, 8, 1), reg_list(8, 0)}}, // T1 + {"ldmia", 2, Pattern(0xC800, high_bits(5), true), Operands{reg(3, 8, 1), reg_list(8, 0)}}, // T1 + {"ldmfd", 2, Pattern(0xC800, high_bits(5), true), Operands{reg(3, 8, 1), reg_list(8, 0)}}, // T1 {"lsls", 2, Pattern(0x0000, high_bits(5)), Operands{reg(3, 0), reg(3, 3), imm(5, 6, 1, 0, {0})}}, {"mov", 2, Pattern(0x4600, high_bits(8)), Operands{reg(0x87), reg(4, 3)}}, // T1 |