diff options
Diffstat (limited to 'asm/intel64/sal_shl.cpp')
| -rw-r--r-- | asm/intel64/sal_shl.cpp | 30 |
1 files changed, 28 insertions, 2 deletions
diff --git a/asm/intel64/sal_shl.cpp b/asm/intel64/sal_shl.cpp index 8dbfb24..50a43cf 100644 --- a/asm/intel64/sal_shl.cpp +++ b/asm/intel64/sal_shl.cpp @@ -18,7 +18,8 @@ Op_sal::Op_sal(const Asm::Args& args) machine_code = std::vector<uint8_t>{ 0xD1 } + ModRM("/4", std::any_cast<Asm::Args::Register32>(args[0]).name()); } else if (args[0].type() == typeid(Asm::Args::Register64)) { // sal reg64, 1 machine_code = REX("W") + std::vector<uint8_t>{ 0xD1 } + ModRM("/4", std::any_cast<Asm::Args::Register64>(args[0]).name()); - } + } else + throw std::runtime_error("SHL: Unsupported first argument type"); } else { // general version >= 2 bits shift if (args[0].type() == typeid(Asm::Args::Register8)) { // sal reg8, imm8 machine_code = std::vector<uint8_t>{ 0xC0 } + ModRM("/4", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset; @@ -26,9 +27,25 @@ Op_sal::Op_sal(const Asm::Args& args) machine_code = std::vector<uint8_t>{ 0xC1 } + ModRM("/4", std::any_cast<Asm::Args::Register32>(args[0]).name()) + shift_offset; } else if (args[0].type() == typeid(Asm::Args::Register64)) { // sal reg64, imm8 machine_code = REX("W") + std::vector<uint8_t>{ 0xC1 } + ModRM("/4", std::any_cast<Asm::Args::Register64>(args[0]).name()) + shift_offset; - } + } else + throw std::runtime_error("SHL: Unsupported first argument type"); } + } else if (args[1].type() == typeid(Asm::Args::Register8)) { + std::string arg1{std::any_cast<Asm::Args::Register8>(args[1]).name()}; + if (arg1 != "cl") + throw std::runtime_error("SHL: Second register argument must be cl"); + + if (args[0].type() == typeid(Asm::Args::Register8)) { // sal reg8, cl + machine_code = std::vector<uint8_t>{ 0xD2 } + ModRM("/4", std::any_cast<Asm::Args::Register8>(args[0]).name()); + } else if (args[0].type() == typeid(Asm::Args::Register16)) { // sal reg16, cl + machine_code = OpSizePrefix() + std::vector<uint8_t>{ 0xD3 } + ModRM("/4", std::any_cast<Asm::Args::Register16>(args[0]).name()); + } else if (args[0].type() == typeid(Asm::Args::Register32)) { // sal reg32, cl + machine_code = std::vector<uint8_t>{ 0xD3 } + ModRM("/4", std::any_cast<Asm::Args::Register32>(args[0]).name()); + } else if (args[0].type() == typeid(Asm::Args::Register64)) { // sal reg64, cl + machine_code = REX("W") + std::vector<uint8_t>{ 0xD3 } + ModRM("/4", std::any_cast<Asm::Args::Register64>(args[0]).name()); + } else + throw std::runtime_error("SHL: Unsupported first argument type"); } else { throw std::runtime_error("Unimplemented: sal(shl) "s + args[0].type().name() + " "s + args[1].type().name()); } @@ -72,6 +89,15 @@ bool registered { }) && registerOp(mangleName<Asm::Args::Mem64Ptr64, Asm::Args::Immediate8>("shl"), [](const Asm::Args& args) -> std::shared_ptr<Op>{ return std::make_shared<Op_sal>(args); + }) && + registerOp(mangleName<Asm::Args::Register8, Asm::Args::Register8>("shl"), [](const Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_sal>(args); + }) && + registerOp(mangleName<Asm::Args::Register16, Asm::Args::Register8>("shl"), [](const Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_sal>(args); + }) && + registerOp(mangleName<Asm::Args::Register32, Asm::Args::Register8>("shl"), [](const Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_sal>(args); }) }; |