summaryrefslogtreecommitdiffhomepage
path: root/asm/intel64/imul.cpp
blob: 4df857729bcf52b65ce525ab6e988289dd68330c (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
#include "imul.h"

#include "codes.h"

#include <asm/assembler.h>
#include <asm/operators.h>

#include <asm/intel64/codes.h>

using namespace std::string_literals;

Op_imul::Op_imul(Asm::Args& args)
{
 if (args[0].type() == typeid(Asm::Args::Register8)) { // imul reg8 (accu is ax <- al)
  machine_code = std::vector<uint8_t>{ 0xF6 } +
   ModRM("/5", std::any_cast<Asm::Args::Register8>(args[0]).name());
 } else if (args[0].type() == typeid(Asm::Args::Register32)) { // imul reg32 (accu is edx:eax <- eax)
  machine_code = std::vector<uint8_t>{ 0xF7 } +
   ModRM("/5", std::any_cast<Asm::Args::Register32>(args[0]).name());
 } else if (args[0].type() == typeid(Asm::Args::Register64)) { // imul reg64 (accu is rdx:rax <- rax)
  machine_code = REX("W") + std::vector<uint8_t>{ 0xF7 } +
   ModRM("/5", std::any_cast<Asm::Args::Register64>(args[0]).name());
 } else {
  throw std::runtime_error("Unimplemented: imul "s + args[0].type().name());
 }
}

namespace {

bool registered {
 registerOp(mangleName<Asm::Args::Register8>("imul"), [](Asm::Args& args) -> std::shared_ptr<Op>{
               return std::make_shared<Op_imul>(args);
            }) &&
 registerOp(mangleName<Asm::Args::Register32>("imul"), [](Asm::Args& args) -> std::shared_ptr<Op>{
               return std::make_shared<Op_imul>(args);
            }) &&
 registerOp(mangleName<Asm::Args::Register64>("imul"), [](Asm::Args& args) -> std::shared_ptr<Op>{
               return std::make_shared<Op_imul>(args);
            })
};

}