Implement shl reg, cl

2 files changed, 35 insertions, 7 deletions

diff --git a/asm/intel64/encode.cpp b/asm/intel64/encode.cpp
index 6c18d1c..0d7eacb 100644
--- a/asm/intel64/encode.cpp
+++ b/asm/intel64/encode.cpp
@@ -171,7 +171,7 @@ std::vector<std::shared_ptr<Chunk>> makeDivValue(const FlowGraph::Data& data, co
   throw std::runtime_error("ICE: Unsupported type for operand data at div: "s + demangle(typeid(data_storage)));
 }
 
-std::shared_ptr<Op> makeShiftLeftValue(const FlowGraph::Data& data, const FlowGraph::Graph& graph)
+std::vector<std::shared_ptr<Chunk>> makeShiftLeftValue(const FlowGraph::Data& data, const FlowGraph::Graph& graph)
 {
  if (data.type() != FlowGraph::DataType::Int) {
   throw std::runtime_error("Bad type for operand: "s + std::to_string(int(data.type())));
@@ -189,13 +189,15 @@ std::shared_ptr<Op> makeShiftLeftValue(const FlowGraph::Data& data, const FlowGr
   uint32_t immediate = endian::from_little32(value.value());
   immediate = std::min(immediate, uint32_t(0xFF));
 
-  return makeOp("shl", Asm::Args{{Asm::Args::Register32("eax"), Asm::Args::Immediate8(static_cast<uint8_t>(immediate))}});
+  return {makeOp("shl", Asm::Args{{Asm::Args::Register32("eax"), Asm::Args::Immediate8(static_cast<uint8_t>(immediate))}})};
  } else if (typeid(data_storage) == typeid(FlowGraph::TemporaryStorage)) {
   //FlowGraph::TemporaryStorage& storage {dynamic_cast<FlowGraph::TemporaryStorage&>(data_storage)};
 
   index_t index { graph.scope()->indexOfData(data)};
-  // makeOp("mov", Asm::Args{{Asm::Args::Register32("ecx"), Asm::Args::Mem32Ptr64("rbp", int32_t(index + 1) * -4)}}); // TODO: return list of ops; limit ecx to 0xff; implement shr x, cl
-  return makeOp("nop");//makeOp("shl", Asm::Args{{Asm::Args::Register32("eax"), Asm::Args::Register8("cl")}});
+  std::vector<std::shared_ptr<Chunk>> result;
+  result.push_back(makeOp("mov", Asm::Args{{Asm::Args::Register32("ecx"), Asm::Args::Mem32Ptr64("rbp", int32_t(index + 1) * -4)}})); // TODO: limit ecx to 0xff
+  result.push_back(makeOp("shl", Asm::Args{{Asm::Args::Register32("eax"), Asm::Args::Register8("cl")}}));
+  return result;
  } else
   throw std::runtime_error("ICE: Unsupported type for operand data at shift left: "s + demangle(typeid(data_storage)));
 }
@@ -270,7 +272,7 @@ void Asm::toMachineCode(const FlowGraph::Graph& graph, Segment& segment)
      segment.push_back(makeStoreValue(operands[0], graph));
     } else if (op.type() == FlowGraph::BinaryOperationType::ShiftLeft) {
      segment.push_back(makeLoadValue(operands[1], graph));
-     segment.push_back(makeShiftLeftValue(operands[2], graph));
+     segment.append(makeShiftLeftValue(operands[2], graph));
      segment.push_back(makeStoreValue(operands[0], graph));
     } else
      throw std::runtime_error("ICE: Asm: Unsupported binary operation type: "s + std::to_string(static_cast<int>(op.type())));
diff --git a/asm/intel64/sal_shl.cpp b/asm/intel64/sal_shl.cpp
index 8dbfb24..50a43cf 100644
--- a/asm/intel64/sal_shl.cpp
+++ b/asm/intel64/sal_shl.cpp
@@ -18,7 +18,8 @@ Op_sal::Op_sal(const Asm::Args& args)
     machine_code = std::vector<uint8_t>{ 0xD1 } + ModRM("/4", std::any_cast<Asm::Args::Register32>(args[0]).name());
    } else if (args[0].type() == typeid(Asm::Args::Register64)) { // sal reg64, 1
     machine_code = REX("W") + std::vector<uint8_t>{ 0xD1 } + ModRM("/4", std::any_cast<Asm::Args::Register64>(args[0]).name());
-   }
+   } else
+    throw std::runtime_error("SHL: Unsupported first argument type");
   } else { // general version >= 2 bits shift
    if (args[0].type() == typeid(Asm::Args::Register8)) { // sal reg8, imm8
     machine_code = std::vector<uint8_t>{ 0xC0 } + ModRM("/4", std::any_cast<Asm::Args::Register8>(args[0]).name()) + shift_offset;
@@ -26,9 +27,25 @@ Op_sal::Op_sal(const Asm::Args& args)
     machine_code = std::vector<uint8_t>{ 0xC1 } + ModRM("/4", std::any_cast<Asm::Args::Register32>(args[0]).name()) + shift_offset;
    } else if (args[0].type() == typeid(Asm::Args::Register64)) { // sal reg64, imm8
     machine_code = REX("W") + std::vector<uint8_t>{ 0xC1 } + ModRM("/4", std::any_cast<Asm::Args::Register64>(args[0]).name()) + shift_offset;
-   }
+   } else
+    throw std::runtime_error("SHL: Unsupported first argument type");
   }
 
+ } else if (args[1].type() == typeid(Asm::Args::Register8)) {
+  std::string arg1{std::any_cast<Asm::Args::Register8>(args[1]).name()};
+  if (arg1 != "cl")
+   throw std::runtime_error("SHL: Second register argument must be cl");
+
+  if (args[0].type() == typeid(Asm::Args::Register8)) { // sal reg8, cl
+   machine_code = std::vector<uint8_t>{ 0xD2 } + ModRM("/4", std::any_cast<Asm::Args::Register8>(args[0]).name());
+  } else if (args[0].type() == typeid(Asm::Args::Register16)) { // sal reg16, cl
+   machine_code = OpSizePrefix() + std::vector<uint8_t>{ 0xD3 } + ModRM("/4", std::any_cast<Asm::Args::Register16>(args[0]).name());
+  } else if (args[0].type() == typeid(Asm::Args::Register32)) { // sal reg32, cl
+   machine_code = std::vector<uint8_t>{ 0xD3 } + ModRM("/4", std::any_cast<Asm::Args::Register32>(args[0]).name());
+  } else if (args[0].type() == typeid(Asm::Args::Register64)) { // sal reg64, cl
+   machine_code = REX("W") + std::vector<uint8_t>{ 0xD3 } + ModRM("/4", std::any_cast<Asm::Args::Register64>(args[0]).name());
+  } else
+   throw std::runtime_error("SHL: Unsupported first argument type");
  } else {
   throw std::runtime_error("Unimplemented: sal(shl) "s + args[0].type().name() + " "s + args[1].type().name());
  }
@@ -72,6 +89,15 @@ bool registered {
                              }) &&
  registerOp(mangleName<Asm::Args::Mem64Ptr64, Asm::Args::Immediate8>("shl"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
                              return std::make_shared<Op_sal>(args);
+                             }) &&
+ registerOp(mangleName<Asm::Args::Register8, Asm::Args::Register8>("shl"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+                             return std::make_shared<Op_sal>(args);
+                             }) &&
+ registerOp(mangleName<Asm::Args::Register16, Asm::Args::Register8>("shl"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+                             return std::make_shared<Op_sal>(args);
+                             }) &&
+ registerOp(mangleName<Asm::Args::Register32, Asm::Args::Register8>("shl"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+                             return std::make_shared<Op_sal>(args);
                              })
 };