Added intel sub, div, idiv

1 files changed, 43 insertions, 0 deletions

diff --git a/asm/intel64/idiv.cpp b/asm/intel64/idiv.cpp
new file mode 100644
index 0000000..c90724f
--- /dev/null
+++ b/asm/intel64/idiv.cpp
@@ -0,0 +1,43 @@
+#include "idiv.h"
+
+#include "codes.h"
+
+#include <asm/assembler.h>
+#include <asm/operators.h>
+
+#include <asm/intel64/codes.h>
+
+using namespace std::string_literals;
+
+Op_idiv::Op_idiv(Asm::Args& args)
+{
+ if (args[0].type() == typeid(Asm::Args::Register8)) { // idiv reg8 (accu is al (remainder=ah) <- ah / reg8)
+  machine_code = std::vector<uint8_t>{ 0xF6 } +
+   ModRM("/7", std::any_cast<Asm::Args::Register8>(args[0]).name());
+ } else if (args[0].type() == typeid(Asm::Args::Register32)) { // idiv reg32 (accu is eax (remainder=edx) <- edx:eax / reg32)
+  machine_code = std::vector<uint8_t>{ 0xF7 } +
+   ModRM("/7", std::any_cast<Asm::Args::Register32>(args[0]).name());
+ } else if (args[0].type() == typeid(Asm::Args::Register64)) { // idiv reg64 (accu is rax (remainder=rdx) <- rdx:rax / reg64)
+  machine_code = REX("W") + std::vector<uint8_t>{ 0xF7 } +
+   ModRM("/7", std::any_cast<Asm::Args::Register64>(args[0]).name());
+ } else {
+  throw std::runtime_error("Unimplemented: idiv "s + args[0].type().name());
+ }
+}
+
+namespace {
+
+bool registered {
+ registerOp(mangleName<Asm::Args::Register8>("idiv"), [](Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_idiv>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Register32>("idiv"), [](Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_idiv>(args);
+            }) &&
+ registerOp(mangleName<Asm::Args::Register64>("idiv"), [](Asm::Args& args) -> std::shared_ptr<Op>{
+               return std::make_shared<Op_idiv>(args);
+            })
+};
+
+}
+