diff options
author | Roland Reichwein <mail@reichwein.it> | 2020-11-09 10:35:00 +0100 |
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committer | Roland Reichwein <mail@reichwein.it> | 2020-11-09 10:35:00 +0100 |
commit | 6ab3715ee2622e293f7c4924511f31347b327e6e (patch) | |
tree | eca588d3d8c320cb25f209b76db91b95cd9f5614 /asm/intel64/inc.cpp | |
parent | 1ac8ab06e9aad3b6d22685255459d71cb49e1f28 (diff) |
Implement inc instruction, support 64 bit regs
Diffstat (limited to 'asm/intel64/inc.cpp')
-rw-r--r-- | asm/intel64/inc.cpp | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/asm/intel64/inc.cpp b/asm/intel64/inc.cpp new file mode 100644 index 0000000..3df9104 --- /dev/null +++ b/asm/intel64/inc.cpp @@ -0,0 +1,43 @@ +#include "inc.h" + +#include "codes.h" + +#include <asm/assembler.h> +#include <asm/operators.h> + +#include <asm/intel64/codes.h> + +using namespace std::string_literals; + +Op_inc::Op_inc(Asm::Args& args) +{ + if (args[0].type() == typeid(Asm::Args::Register8)) { // inc reg8 + machine_code = std::vector<uint8_t>{ 0xFE } + + ModRM("/0", std::any_cast<Asm::Args::Register8>(args[0]).name()); + } else if (args[0].type() == typeid(Asm::Args::Register32)) { // inc reg32 + machine_code = std::vector<uint8_t>{ 0xFF } + + ModRM("/0", std::any_cast<Asm::Args::Register32>(args[0]).name()); + } else if (args[0].type() == typeid(Asm::Args::Register64)) { // inc reg64 + machine_code = REX("W") + std::vector<uint8_t>{ 0xFF } + + ModRM("/0", std::any_cast<Asm::Args::Register64>(args[0]).name()); + } else { + throw std::runtime_error("Unimplemented: inc "s + args[0].type().name()); + } +} + +namespace { + +bool registered { + registerOp(mangleName<Asm::Args::Register8>("inc"), [](Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_inc>(args); + }) && + registerOp(mangleName<Asm::Args::Register32>("inc"), [](Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_inc>(args); + }) && + registerOp(mangleName<Asm::Args::Register64>("inc"), [](Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_inc>(args); + }) +}; + +} + |