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authorRoland Reichwein <mail@reichwein.it>2020-11-22 13:00:06 +0100
committerRoland Reichwein <mail@reichwein.it>2020-11-22 13:00:06 +0100
commit1fae63de23320a1663b7c591e247ad81852ab6dc (patch)
treebfe539b7eeb5a4d7b68aa1bf853898d60e34f784 /asm/intel64/mov.cpp
parent739297d8895b08a9ecd8e81b01b7ba8e8dc4a8ae (diff)
Support 16-bit short
Diffstat (limited to 'asm/intel64/mov.cpp')
-rw-r--r--asm/intel64/mov.cpp8
1 files changed, 8 insertions, 0 deletions
diff --git a/asm/intel64/mov.cpp b/asm/intel64/mov.cpp
index 805675a..9382a76 100644
--- a/asm/intel64/mov.cpp
+++ b/asm/intel64/mov.cpp
@@ -16,6 +16,11 @@ Op_mov::Op_mov(const Asm::Args& args)
machine_code = std::vector<uint8_t>{ 0x88 } +
ModRM(std::any_cast<Asm::Args::Register8>(args[1]).name(), std::any_cast<Asm::Args::Register8>(args[0]).name());
+ } else if (args[0].type() == typeid(Asm::Args::Register16) && args[1].type() == typeid(Asm::Args::Register16)) { // mov reg16, reg16
+ // r/m16, r16: ModRM:r/m (w), ModRM:reg (r)
+ machine_code = OpSizePrefix() + std::vector<uint8_t>{ 0x89 } +
+ ModRM(std::any_cast<Asm::Args::Register16>(args[1]).name(), std::any_cast<Asm::Args::Register16>(args[0]).name());
+
} else if (args[0].type() == typeid(Asm::Args::Register32) && args[1].type() == typeid(Asm::Args::Register32)) { // mov reg32, reg32
// r/m32, r32: ModRM:r/m (w), ModRM:reg (r)
machine_code = std::vector<uint8_t>{ 0x89 } +
@@ -79,6 +84,9 @@ bool registered {
registerOp(mangleName<Asm::Args::Register8, Asm::Args::Register8>("mov"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
return std::make_shared<Op_mov>(args);
}) &&
+ registerOp(mangleName<Asm::Args::Register16, Asm::Args::Register16>("mov"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+ return std::make_shared<Op_mov>(args);
+ }) &&
registerOp(mangleName<Asm::Args::Register32, Asm::Args::Register32>("mov"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
return std::make_shared<Op_mov>(args);
}) &&