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authorRoland Reichwein <mail@reichwein.it>2020-11-21 21:38:56 +0100
committerRoland Reichwein <mail@reichwein.it>2020-11-21 21:38:56 +0100
commit39bccce4fdd1d5ebe312321c963e0325e4d696c5 (patch)
tree6663c36c77a7209bb2318d1f20d2b23dcf5782e0 /asm/intel64/mul.cpp
parent7fd9bbf4ea1ba5ea1b30e9ba3039195ab40c246a (diff)
Bugfixing of stack (WIP)
Diffstat (limited to 'asm/intel64/mul.cpp')
-rw-r--r--asm/intel64/mul.cpp9
1 files changed, 6 insertions, 3 deletions
diff --git a/asm/intel64/mul.cpp b/asm/intel64/mul.cpp
index 5825e2a..14810dc 100644
--- a/asm/intel64/mul.cpp
+++ b/asm/intel64/mul.cpp
@@ -21,14 +21,17 @@ Op_mul::Op_mul(const Asm::Args& args)
machine_code = REX("W") + std::vector<uint8_t>{ 0xF7 } +
ModRM("/4", std::any_cast<Asm::Args::Register64>(args[0]).name());
} else if (args[0].type() == typeid(Asm::Args::Mem8Ptr64)) { // mul byte ptr [reg64] (accu is ax <- al)
+ Asm::Args::Mem8Ptr64 ptr{std::any_cast<Asm::Args::Mem8Ptr64>(args[0])};
machine_code = std::vector<uint8_t>{ 0xF6 } +
- ModRM("/4", std::any_cast<Asm::Args::Mem8Ptr64>(args[0]).reg());
+ ModRM("/4", ptr.reg(), ptr.offs());
} else if (args[0].type() == typeid(Asm::Args::Mem32Ptr64)) { // mul dword ptr [reg64] (accu is edx:eax <- eax)
+ Asm::Args::Mem32Ptr64 ptr{std::any_cast<Asm::Args::Mem32Ptr64>(args[0])};
machine_code = std::vector<uint8_t>{ 0xF7 } +
- ModRM("/4", std::any_cast<Asm::Args::Mem32Ptr64>(args[0]).reg());
+ ModRM("/4", ptr.reg(), ptr.offs());
} else if (args[0].type() == typeid(Asm::Args::Mem64Ptr64)) { // mul qword ptr [reg64] (accu is rdx:rax <- rax)
+ Asm::Args::Mem64Ptr64 ptr{std::any_cast<Asm::Args::Mem64Ptr64>(args[0])};
machine_code = REX("W") + std::vector<uint8_t>{ 0xF7 } +
- ModRM("/4", std::any_cast<Asm::Args::Mem64Ptr64>(args[0]).reg());
+ ModRM("/4", ptr.reg(), ptr.offs());
} else {
throw std::runtime_error("Unimplemented: mul "s + args[0].type().name());
}