diff options
Diffstat (limited to 'asm/intel64/mul.cpp')
| -rw-r--r-- | asm/intel64/mul.cpp | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/asm/intel64/mul.cpp b/asm/intel64/mul.cpp index 502b1d9..5825e2a 100644 --- a/asm/intel64/mul.cpp +++ b/asm/intel64/mul.cpp @@ -20,6 +20,15 @@ Op_mul::Op_mul(const Asm::Args& args) } else if (args[0].type() == typeid(Asm::Args::Register64)) { // mul reg64 (accu is rdx:rax <- rax) machine_code = REX("W") + std::vector<uint8_t>{ 0xF7 } + ModRM("/4", std::any_cast<Asm::Args::Register64>(args[0]).name()); + } else if (args[0].type() == typeid(Asm::Args::Mem8Ptr64)) { // mul byte ptr [reg64] (accu is ax <- al) + machine_code = std::vector<uint8_t>{ 0xF6 } + + ModRM("/4", std::any_cast<Asm::Args::Mem8Ptr64>(args[0]).reg()); + } else if (args[0].type() == typeid(Asm::Args::Mem32Ptr64)) { // mul dword ptr [reg64] (accu is edx:eax <- eax) + machine_code = std::vector<uint8_t>{ 0xF7 } + + ModRM("/4", std::any_cast<Asm::Args::Mem32Ptr64>(args[0]).reg()); + } else if (args[0].type() == typeid(Asm::Args::Mem64Ptr64)) { // mul qword ptr [reg64] (accu is rdx:rax <- rax) + machine_code = REX("W") + std::vector<uint8_t>{ 0xF7 } + + ModRM("/4", std::any_cast<Asm::Args::Mem64Ptr64>(args[0]).reg()); } else { throw std::runtime_error("Unimplemented: mul "s + args[0].type().name()); } @@ -36,6 +45,15 @@ bool registered { }) && registerOp(mangleName<Asm::Args::Register64>("mul"), [](const Asm::Args& args) -> std::shared_ptr<Op>{ return std::make_shared<Op_mul>(args); + }) && + registerOp(mangleName<Asm::Args::Mem8Ptr64>("mul"), [](const Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_mul>(args); + }) && + registerOp(mangleName<Asm::Args::Mem32Ptr64>("mul"), [](const Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_mul>(args); + }) && + registerOp(mangleName<Asm::Args::Mem64Ptr64>("mul"), [](const Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_mul>(args); }) }; |