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-rw-r--r--asm/intel64/div.cpp18
-rw-r--r--asm/intel64/encode.cpp41
-rw-r--r--asm/intel64/mul.cpp18
3 files changed, 77 insertions, 0 deletions
diff --git a/asm/intel64/div.cpp b/asm/intel64/div.cpp
index 9ca24e9..1e98b7b 100644
--- a/asm/intel64/div.cpp
+++ b/asm/intel64/div.cpp
@@ -20,6 +20,15 @@ Op_div::Op_div(const Asm::Args& args)
} else if (args[0].type() == typeid(Asm::Args::Register64)) { // div reg64 (accu is rax (remainder=rdx) <- rdx:rax / reg64)
machine_code = REX("W") + std::vector<uint8_t>{ 0xF7 } +
ModRM("/6", std::any_cast<Asm::Args::Register64>(args[0]).name());
+ } else if (args[0].type() == typeid(Asm::Args::Mem8Ptr64)) { // div byte ptr [reg64] (accu is al (remainder=ah) <- ah / x)
+ machine_code = std::vector<uint8_t>{ 0xF6 } +
+ ModRM("/6", std::any_cast<Asm::Args::Mem8Ptr64>(args[0]).reg());
+ } else if (args[0].type() == typeid(Asm::Args::Mem32Ptr64)) { // div dword ptr [reg64] (accu is eax (remainder=edx) <- edx:eax / x)
+ machine_code = std::vector<uint8_t>{ 0xF7 } +
+ ModRM("/6", std::any_cast<Asm::Args::Mem32Ptr64>(args[0]).reg());
+ } else if (args[0].type() == typeid(Asm::Args::Mem64Ptr64)) { // div qword ptr [reg64] (accu is rax (remainder=rdx) <- rdx:rax / x)
+ machine_code = REX("W") + std::vector<uint8_t>{ 0xF7 } +
+ ModRM("/6", std::any_cast<Asm::Args::Mem64Ptr64>(args[0]).reg());
} else {
throw std::runtime_error("Unimplemented: div "s + args[0].type().name());
}
@@ -36,6 +45,15 @@ bool registered {
}) &&
registerOp(mangleName<Asm::Args::Register64>("div"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
return std::make_shared<Op_div>(args);
+ }) &&
+ registerOp(mangleName<Asm::Args::Mem8Ptr64>("div"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+ return std::make_shared<Op_div>(args);
+ }) &&
+ registerOp(mangleName<Asm::Args::Mem32Ptr64>("div"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+ return std::make_shared<Op_div>(args);
+ }) &&
+ registerOp(mangleName<Asm::Args::Mem64Ptr64>("div"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+ return std::make_shared<Op_div>(args);
})
};
diff --git a/asm/intel64/encode.cpp b/asm/intel64/encode.cpp
index 1b35d89..a2434fd 100644
--- a/asm/intel64/encode.cpp
+++ b/asm/intel64/encode.cpp
@@ -114,6 +114,36 @@ std::vector<std::shared_ptr<Chunk>> makeMulValue(const FlowGraph::Data& data, co
throw std::runtime_error("ICE: Unsupported type for operand data at mul: "s + demangle(typeid(data_storage)));
}
+std::vector<std::shared_ptr<Chunk>> makeDivValue(const FlowGraph::Data& data, const FlowGraph::Graph& graph)
+{
+ if (data.type() != FlowGraph::DataType::Int) {
+ throw std::runtime_error("Bad type for operand: "s + std::to_string(int(data.type())));
+ }
+
+ if (!data.storage())
+ throw std::runtime_error("ICE: Operand storage is 0");
+
+ auto& data_storage{*data.storage()};
+ if (typeid(data_storage) == typeid(FlowGraph::Constant)) {
+ FlowGraph::Constant& value {dynamic_cast<FlowGraph::Constant&>(data_storage)};
+ if (value.value().size() < sizeof(uint32_t))
+ throw std::runtime_error("ICE: Int data from operand needs at least 4 bytes, got "s + std::to_string(value.value().size()));
+
+ uint32_t immediate = from_little_endian(value.value());
+
+ return {{
+ makeOp("mov", Asm::Args{{Asm::Args::Register32("ebx"), Asm::Args::Immediate32(immediate)}}),
+ makeOp("div", Asm::Args{{Asm::Args::Register32("ebx")}})
+ }};
+ } else if (typeid(data_storage) == typeid(FlowGraph::TemporaryStorage)) {
+ //FlowGraph::TemporaryStorage& storage {dynamic_cast<FlowGraph::TemporaryStorage&>(data_storage)};
+
+ index_t index { graph.scope()->indexOfData(data)};
+ return {{makeOp("div", Asm::Args{{Asm::Args::Mem32Ptr64("rbp", int32_t(index) * -4)}})}};
+ } else
+ throw std::runtime_error("ICE: Unsupported type for operand data at div: "s + demangle(typeid(data_storage)));
+}
+
} // namespace
void Asm::toMachineCode(const FlowGraph::Graph& graph, Segment& segment)
@@ -165,6 +195,17 @@ void Asm::toMachineCode(const FlowGraph::Graph& graph, Segment& segment)
segment.push_back(makeLoadValue(operands[1], graph));
segment.append(makeMulValue(operands[2], graph));
segment.push_back(makeStoreValue(operands[0], graph));
+ } else if (op.type() == FlowGraph::BinaryOperationType::Divide) {
+ segment.push_back(makeLoadValue(operands[1], graph));
+ segment.append(parseAsm("xor edx, edx"));
+ segment.append(makeDivValue(operands[2], graph));
+ segment.push_back(makeStoreValue(operands[0], graph));
+ } else if (op.type() == FlowGraph::BinaryOperationType::Modulo) {
+ segment.push_back(makeLoadValue(operands[1], graph));
+ segment.append(parseAsm("xor edx, edx"));
+ segment.append(makeDivValue(operands[2], graph));
+ segment.append(parseAsm("mov eax, edx")); // remainder is in edx
+ segment.push_back(makeStoreValue(operands[0], graph));
} else
throw std::runtime_error("ICE: Asm: Unsupported binary operation type: "s + std::to_string(static_cast<int>(op.type())));
diff --git a/asm/intel64/mul.cpp b/asm/intel64/mul.cpp
index 502b1d9..5825e2a 100644
--- a/asm/intel64/mul.cpp
+++ b/asm/intel64/mul.cpp
@@ -20,6 +20,15 @@ Op_mul::Op_mul(const Asm::Args& args)
} else if (args[0].type() == typeid(Asm::Args::Register64)) { // mul reg64 (accu is rdx:rax <- rax)
machine_code = REX("W") + std::vector<uint8_t>{ 0xF7 } +
ModRM("/4", std::any_cast<Asm::Args::Register64>(args[0]).name());
+ } else if (args[0].type() == typeid(Asm::Args::Mem8Ptr64)) { // mul byte ptr [reg64] (accu is ax <- al)
+ machine_code = std::vector<uint8_t>{ 0xF6 } +
+ ModRM("/4", std::any_cast<Asm::Args::Mem8Ptr64>(args[0]).reg());
+ } else if (args[0].type() == typeid(Asm::Args::Mem32Ptr64)) { // mul dword ptr [reg64] (accu is edx:eax <- eax)
+ machine_code = std::vector<uint8_t>{ 0xF7 } +
+ ModRM("/4", std::any_cast<Asm::Args::Mem32Ptr64>(args[0]).reg());
+ } else if (args[0].type() == typeid(Asm::Args::Mem64Ptr64)) { // mul qword ptr [reg64] (accu is rdx:rax <- rax)
+ machine_code = REX("W") + std::vector<uint8_t>{ 0xF7 } +
+ ModRM("/4", std::any_cast<Asm::Args::Mem64Ptr64>(args[0]).reg());
} else {
throw std::runtime_error("Unimplemented: mul "s + args[0].type().name());
}
@@ -36,6 +45,15 @@ bool registered {
}) &&
registerOp(mangleName<Asm::Args::Register64>("mul"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
return std::make_shared<Op_mul>(args);
+ }) &&
+ registerOp(mangleName<Asm::Args::Mem8Ptr64>("mul"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+ return std::make_shared<Op_mul>(args);
+ }) &&
+ registerOp(mangleName<Asm::Args::Mem32Ptr64>("mul"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+ return std::make_shared<Op_mul>(args);
+ }) &&
+ registerOp(mangleName<Asm::Args::Mem64Ptr64>("mul"), [](const Asm::Args& args) -> std::shared_ptr<Op>{
+ return std::make_shared<Op_mul>(args);
})
};
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