diff options
Diffstat (limited to 'asm/intel64')
-rw-r--r-- | asm/intel64/all_ops.h | 3 | ||||
-rw-r--r-- | asm/intel64/dec.cpp | 43 | ||||
-rw-r--r-- | asm/intel64/dec.h | 31 | ||||
-rw-r--r-- | asm/intel64/imul.cpp | 43 | ||||
-rw-r--r-- | asm/intel64/imul.h | 31 | ||||
-rw-r--r-- | asm/intel64/mul.cpp | 43 | ||||
-rw-r--r-- | asm/intel64/mul.h | 31 |
7 files changed, 225 insertions, 0 deletions
diff --git a/asm/intel64/all_ops.h b/asm/intel64/all_ops.h index 59ce624..9f41c5d 100644 --- a/asm/intel64/all_ops.h +++ b/asm/intel64/all_ops.h @@ -1,10 +1,13 @@ #pragma once #include "add.h" +#include "dec.h" +#include "imul.h" #include "inc.h" #include "int.h" #include "jmp.h" #include "mov.h" +#include "mul.h" #include "nop.h" #include "ret.h" #include "xor.h" diff --git a/asm/intel64/dec.cpp b/asm/intel64/dec.cpp new file mode 100644 index 0000000..dab603a --- /dev/null +++ b/asm/intel64/dec.cpp @@ -0,0 +1,43 @@ +#include "dec.h" + +#include "codes.h" + +#include <asm/assembler.h> +#include <asm/operators.h> + +#include <asm/intel64/codes.h> + +using namespace std::string_literals; + +Op_dec::Op_dec(Asm::Args& args) +{ + if (args[0].type() == typeid(Asm::Args::Register8)) { // dec reg8 + machine_code = std::vector<uint8_t>{ 0xFE } + + ModRM("/1", std::any_cast<Asm::Args::Register8>(args[0]).name()); + } else if (args[0].type() == typeid(Asm::Args::Register32)) { // dec reg32 + machine_code = std::vector<uint8_t>{ 0xFF } + + ModRM("/1", std::any_cast<Asm::Args::Register32>(args[0]).name()); + } else if (args[0].type() == typeid(Asm::Args::Register64)) { // dec reg64 + machine_code = REX("W") + std::vector<uint8_t>{ 0xFF } + + ModRM("/1", std::any_cast<Asm::Args::Register64>(args[0]).name()); + } else { + throw std::runtime_error("Unimplemented: dec "s + args[0].type().name()); + } +} + +namespace { + +bool registered { + registerOp(mangleName<Asm::Args::Register8>("dec"), [](Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_dec>(args); + }) && + registerOp(mangleName<Asm::Args::Register32>("dec"), [](Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_dec>(args); + }) && + registerOp(mangleName<Asm::Args::Register64>("dec"), [](Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_dec>(args); + }) +}; + +} + diff --git a/asm/intel64/dec.h b/asm/intel64/dec.h new file mode 100644 index 0000000..293ba8d --- /dev/null +++ b/asm/intel64/dec.h @@ -0,0 +1,31 @@ +// Decrement Register + +#pragma once + +#include <asm/assembler.h> + +class Op_dec: public Op +{ +public: + Op_dec(Asm::Args& args); + +public: + std::vector<uint8_t> getCode() override + { + return machine_code; + } + + size_t size() override + { + return machine_code.size(); + } + + bool optimize() override ///< returns true if changed + { + return false; + } + +protected: + std::vector<uint8_t> machine_code; +}; + diff --git a/asm/intel64/imul.cpp b/asm/intel64/imul.cpp new file mode 100644 index 0000000..4df8577 --- /dev/null +++ b/asm/intel64/imul.cpp @@ -0,0 +1,43 @@ +#include "imul.h" + +#include "codes.h" + +#include <asm/assembler.h> +#include <asm/operators.h> + +#include <asm/intel64/codes.h> + +using namespace std::string_literals; + +Op_imul::Op_imul(Asm::Args& args) +{ + if (args[0].type() == typeid(Asm::Args::Register8)) { // imul reg8 (accu is ax <- al) + machine_code = std::vector<uint8_t>{ 0xF6 } + + ModRM("/5", std::any_cast<Asm::Args::Register8>(args[0]).name()); + } else if (args[0].type() == typeid(Asm::Args::Register32)) { // imul reg32 (accu is edx:eax <- eax) + machine_code = std::vector<uint8_t>{ 0xF7 } + + ModRM("/5", std::any_cast<Asm::Args::Register32>(args[0]).name()); + } else if (args[0].type() == typeid(Asm::Args::Register64)) { // imul reg64 (accu is rdx:rax <- rax) + machine_code = REX("W") + std::vector<uint8_t>{ 0xF7 } + + ModRM("/5", std::any_cast<Asm::Args::Register64>(args[0]).name()); + } else { + throw std::runtime_error("Unimplemented: imul "s + args[0].type().name()); + } +} + +namespace { + +bool registered { + registerOp(mangleName<Asm::Args::Register8>("imul"), [](Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_imul>(args); + }) && + registerOp(mangleName<Asm::Args::Register32>("imul"), [](Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_imul>(args); + }) && + registerOp(mangleName<Asm::Args::Register64>("imul"), [](Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_imul>(args); + }) +}; + +} + diff --git a/asm/intel64/imul.h b/asm/intel64/imul.h new file mode 100644 index 0000000..387d87f --- /dev/null +++ b/asm/intel64/imul.h @@ -0,0 +1,31 @@ +// Multiply Signed Integer + +#pragma once + +#include <asm/assembler.h> + +class Op_imul: public Op +{ +public: + Op_imul(Asm::Args& args); + +public: + std::vector<uint8_t> getCode() override + { + return machine_code; + } + + size_t size() override + { + return machine_code.size(); + } + + bool optimize() override ///< returns true if changed + { + return false; + } + +protected: + std::vector<uint8_t> machine_code; +}; + diff --git a/asm/intel64/mul.cpp b/asm/intel64/mul.cpp new file mode 100644 index 0000000..e4c3489 --- /dev/null +++ b/asm/intel64/mul.cpp @@ -0,0 +1,43 @@ +#include "mul.h" + +#include "codes.h" + +#include <asm/assembler.h> +#include <asm/operators.h> + +#include <asm/intel64/codes.h> + +using namespace std::string_literals; + +Op_mul::Op_mul(Asm::Args& args) +{ + if (args[0].type() == typeid(Asm::Args::Register8)) { // mul reg8 (accu is ax <- al) + machine_code = std::vector<uint8_t>{ 0xF6 } + + ModRM("/4", std::any_cast<Asm::Args::Register8>(args[0]).name()); + } else if (args[0].type() == typeid(Asm::Args::Register32)) { // mul reg32 (accu is edx:eax <- eax) + machine_code = std::vector<uint8_t>{ 0xF7 } + + ModRM("/4", std::any_cast<Asm::Args::Register32>(args[0]).name()); + } else if (args[0].type() == typeid(Asm::Args::Register64)) { // mul reg64 (accu is rdx:rax <- rax) + machine_code = REX("W") + std::vector<uint8_t>{ 0xF7 } + + ModRM("/4", std::any_cast<Asm::Args::Register64>(args[0]).name()); + } else { + throw std::runtime_error("Unimplemented: mul "s + args[0].type().name()); + } +} + +namespace { + +bool registered { + registerOp(mangleName<Asm::Args::Register8>("mul"), [](Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_mul>(args); + }) && + registerOp(mangleName<Asm::Args::Register32>("mul"), [](Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_mul>(args); + }) && + registerOp(mangleName<Asm::Args::Register64>("mul"), [](Asm::Args& args) -> std::shared_ptr<Op>{ + return std::make_shared<Op_mul>(args); + }) +}; + +} + diff --git a/asm/intel64/mul.h b/asm/intel64/mul.h new file mode 100644 index 0000000..9ff31d1 --- /dev/null +++ b/asm/intel64/mul.h @@ -0,0 +1,31 @@ +// Multiply Unsigned Integer + +#pragma once + +#include <asm/assembler.h> + +class Op_mul: public Op +{ +public: + Op_mul(Asm::Args& args); + +public: + std::vector<uint8_t> getCode() override + { + return machine_code; + } + + size_t size() override + { + return machine_code.size(); + } + + bool optimize() override ///< returns true if changed + { + return false; + } + +protected: + std::vector<uint8_t> machine_code; +}; + |