Add add

1 files changed, 31 insertions, 0 deletions

diff --git a/asm/intel64/add.cpp b/asm/intel64/add.cpp
new file mode 100644
index 0000000..dc5c704
--- /dev/null
+++ b/asm/intel64/add.cpp
@@ -0,0 +1,31 @@
+#include "add.h"
+
+#include "codes.h"
+
+#include <asm/assembler.h>
+#include <asm/operators.h>
+
+using namespace std::string_literals;
+
+Op_add::Op_add(AsmArgs& args)
+{
+ if (args[0].type() == typeid(Register32) && std::any_cast<Register32>(args[0]).name() == "eax" && args[1].type() == typeid(Immediate32)) { // add eax, imm32
+  machine_code = std::vector<uint8_t>{ 0x05 } + std::any_cast<Immediate32>(args[1]).getCode();
+ } else if (args[0].type() == typeid(Register64) && std::any_cast<Register64>(args[0]).name() == "rax"  && args[1].type() == typeid(Immediate32)) { // add rax, imm32
+  machine_code = REX("W") + std::vector<uint8_t>{ 0x05 } + std::any_cast<Immediate32>(args[1]).getCode();
+ } else {
+  throw std::runtime_error("Unimplemented: add "s + args[0].type().name() + " "s + args[1].type().name());
+ }
+}
+
+namespace {
+
+bool registered0 { registerOp(mangleName<Register32, Immediate32>("add"), [](AsmArgs& args) -> std::shared_ptr<Op>{
+                             return std::make_shared<Op_add>(args);
+                             }) };
+// TODO
+bool registered1 { registerOp(mangleName<Register64, Immediate32>("add"), [](AsmArgs& args) -> std::shared_ptr<Op>{
+                             return std::make_shared<Op_add>(args);
+                             }) };
+
+}